A product Line of
Diodes Incorporated
PI6CDBL401B
4-Output Low Power PCIE GEN1-2-3 Buffer
Features Description
4x 100MHz low power HCSL or LVDS compatible outputs e PTh I6CDBL401B is a 4-output low power buffer for 100MHz
PCIe Gen1, Gen2 and Gen3 applications with integrated output
PCIe 3.0, 2.0 and 1.0 compliant
terminations providing Zo=100. The device has 4 output en -
Programmable output amplitude and slew rate
ables for clock management, and 3 selectable SMBus addresses.
Core supply voltage of 3.3V +/-10%
Output supply voltage of 1.8V, 2.5V and 3.3V
Applications
Industrial ambient operation temperature
PCIe 3.0/2.0/1.0 clock distribution
Available in lead-free package: 32-TQFN
Block Diagram
OE(3:0)#
4
CLK(3:0)
CLK_IN
ZDB PLL
CLK_IN#
SADR_tri
HIBW_BYPM_LOBW#
CONTROL
CKPWRGD_PD#
LOGIC
SDATA_3.3
SCLK_3.3
October 2017
PI6CDBL401B www.diodes.com Diodes Incorporated
111
Document Number DS40392 Rev 4-2 A product Line of
Diodes Incorporated
PI6CDBL401B
Pin Configuration
32 31 30 29 28 27 26 25
HIBW_BYPM_LOBW# 1
24 OE2#
FB_DNC 2
23 CLK2#
FB_DNC# 3
22 CLK2
VDDR3.3 4
21 VDDA3.3
PI6CDBL401B
CLK_IN 5
20 GNDA
CLK_IN# 6
19 CLK1#
GNDR 7
18 CLK1
GNDDIG 8
17 OE1#
9 10 11 12 13 14 15 16
SMBus Address Selection Table
SADR Address + Read / Write bit
0 1101011 1/0
State of SADR on first application of CKPWRGD_PD# M 1101100 1/0
1 1101101 1/0
Power Management Table
CLKx
CKPWRGD_PD# CLK_IN SMBus OEx bit OEx# Pin True O/P Comp. O/P PLL
0 x x x Low Low Off
1
1 Running 0 x Low Low On
1
1 Running 1 0 Running Running On
1
1 Running x 1 Low Low On
1. If bypass mode is selected, the PLL will be off, and outputs will be running
Power Connections PLL Operating Mode
Pin Number Byte1 [7:6] Byte1 [4:3]
HiBW_BypM_LoBW# MODE Readback Control
VDD GND Description
0 PLL Lo BW 00, 10 00, 10
4 7 Input receiver analog
M Bypass 01 01
9 8 Digital Power
1 PLL Hi BW 11 11
16, 25 15, 26, 30 DIF outputs
21 20 PLL Analog
October 2017
PI6CDBL401B www.diodes.com Diodes Incorporated
222
Document Number DS40392 Rev 4-2
SADR_tri
VDDDIG3.3
SCLK_3.3 CKPWRGD_PD#
GND
SDATA_3.3
OE0# OE3#
CLK3#
CLK0
CLK0# CLK3
GND
GND
VDDO1.8 VDDO1.8