PI6CDBL402B
4 -Output Low Power PCIE GEN 1-2-3 Buffer
Description
Features
Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant
Phase jitter filter for PCIe 3.0/ 2.0/ 1.0 application
high-speed, low-noise differential clock buffer designed to be
Low power consumption with independent output power
companion to PCIe 3.0 clock generator. It is backward compat-
supply 1.8V~3.3V
ible with PCIe 1.0 and 2.0 specicfi ation.
Low skew < 60ps
Low cycle-to-cycle jitter - 45ps (typ.) @100MHz
e dTh evice distributes the differential SRC clock from PCIe 3.0
< 1 ps additive RMS phase jitter
clock generator to four differential pairs of clock outputs either
with or without PLL. The clock outputs are controlled by input
Output Enable for all outputs
selection of PWRDWN# and SMBus, SCLK and SDA.
Programmable PLL Bandwidth
100 MHz PLL Mode operation
1 - 400 MHz Bypass Mode operation
3.3V Operation
Packaging (Pb-free and Green):
-28-Pin TSSOP (L28)
Block Diagram Pin Configuration
VDD 28 VDD_A
1
OE_INV
SRC 27 GNDA
2
OE_0 & OE_3
Output
Control
PWRDWN#
26
SRC# 3 NC
OUT0
25
GND 4 OE_INV
OUT0#
VDDO 24 VDDO
5
OUT1
SCLK SMBus
OUT1# OUT0 23 OUT3
6
SDA Controller
22
OUT2 OUT0# 7 OUT3#
OUT2#
21
OE_0 8 OE_3
PLL/BYPASS#
OUT3
OUT1 20 OUT2
SRC 9
OUT3#
SRC#
OUT1# 19 OUT2#
10
VDDO 18 VDDO
11
17
PLL/BYPASS#PLL/BYPASS# 12 PLL_BW#
PLL_BW#
SCLK 16 VDD
13
PLL
SDA 15 PWRDWN#
14
All trademarks are property of their respective owners. www.pericom.com 06/30/15
15-0083 11PI6CDBL402B
4 -Output Low Power PCIE GEN 1-2-3 Buffer
Pin Description
Pin # Pin Name Type Description
2, 3 SRC & SRC# Input 0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active high.
8, 21 OE_0 & OE_3 Input OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
3.3V LVTTL input for inverting the OE and PWRDWN# pins.
25 OE_INV Input When 0 = same stage
When 1 = OE_0, OE_3, PWRDWN# inverted.
0.7V Differential outputs, refer Power Management Table for
6, 7, 9, 10, 19, 20, 22, 23 OUT[0:3] & OUT[0:3]# Output
detail output status
12 PLL/BYPASS# Input 3.3V LVTTL input for selecting fan-out of PLL operation.
13 SCLK Input SMBus compatible SCLOCK input
14 SDA I/O SMBus compatible SDATA
26 NC No Connect
17 PLL_BW# Input 3.3V LVTTL input for selecting the PLL bandwidth
15 PWRDWN# Input 3.3V LVTTL input for Power Down operation, active low
5, 11, 18, 24 V Power Power supply for outputs, range from 1.8V~3.3V
DDO
4 GND Ground Ground for Outputs
27 GNDA Ground Ground for PLL
28 V Power 3.3V Power Supply for PLL
DD_A
1, 16 V Power 3.3V Power Supply for PLL
DD
All trademarks are property of their respective owners. www.pericom.com 06/30/15
15-0083 22