PI6CEQ20200
PCIe Gen2 / Gen3 Buffer
Features Description
PCIe Gen2/ Gen3* compliant clock buffer/ZDB e PTh I6CEQ20200 is a high performance PCIe Gen2/ Gen3
zero delay buffer with two HCSL outputs. Pericoms proprietary
* Gen3 performance only available in Commercial temp
equalization technique used in this device improves signal
Internal equalization for better signal integrity
integrity and makes this device suitable for PCIe Gen2/ Gen3
2 HCSL outputs
applications even when the input from the main clock has to
travel a long distance.
Dual PLL bandwidth for SSC tracking
Cycle-to-Cycle Jitter : 40ps (typ)
Output-to-Output Skew <10ps
3.3V supply voltage
TSSOP-20 packages
Applications
Servers
Embedded computing systems
Networking systems
Block Diagram Pin Configuration (20-Pin TSSOP & 20-Pin QSOP)
1
PLL_BW_SEL
20 VDDA
OE0#
CLK0
2
SRCIN 19 GNDA
CLK0#
3
SRCIN# 18 IRef
SRCIN
EQ
PLL
SRCIN#
4
OE_0# 17
OE_1#
5
VDD
16 VDD
OE1#
PLL_BW_SEL
SCLK Control CLK1
6
SDATA GND
CLK1# 15 GND
7
CLK0 14 CLK1
8
CLK0# 13 CLK1#
9
VDD
12 VDD
10
SDATA
11 SCLK
www.pericom.com Rev B 05/05/15
15-0058 1P I 6 C E Q 20 20 0
PCIe Gen2 / Gen3 Buffer with Equalization
Pin Description
Pin # Pin Name Type Description
1 PLL_BW_SEL Input CMOS input to select the PLL Bandwidth
2, 3 SRCIN, SRCIN# Input HCSL inputs
Output enable for CLK0 and CLK0#. 0 is enabled, 1 is tri-stated.
4 OE_0# Input
Internal pull-down
5, 9, 12, 16 VDD Power 3.3V Power Supply
6, 15 GND Power Ground
7, 8 CLK0, CLK0# Input HCSL output
10 SDATA Input/Output SMBus data
11 SCLK Input SMBus clock input
13, 14 CKL1#, CLK1 Output HCSL output
Output enable for CLK1 and CLK1#. 0 is enabled, 1 is tri-stated.
17 OE_1# Input
Internal pull-down
18 IRef Input External resistor connection for internal current reference
19 GNDA Power Analog and PLL Ground
20 VDDA Power Analog and PLL power supply
www.pericom.com Rev B 05/05/15
15-0058 2