PI6CV857B
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
Product Description
Operating Frequency up to 200 MHz and exceeds PC2700
PI6CV857B PLL clock device is developed for registered DDR DIMM
RDIMM specification
applications This PLL Clock Buffer is designed for 2.5 V and 2.5V
DDQ
Distributes one differential clock input pair to ten differential AV operation and differential data input and output levels.
DD
clock output pairs. The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9],
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Y[0:9]) and one differential pair feedback clock outputs
Input PWRDWN: LVCMOS
(FBOUT,FBOUT) . The clock outputs are controlled by the input
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
External feedback pins (FBIN,FBIN) are used to
LVCMOS input (PWRDWN) and the Analog Power input (AV ).
DD
synchronize the outputs to the clock input.
When input PWRDWN is low while power is applied, the input
Operates at AV = 2.5V for core circuit and internal PLL,
DD
receivers are disabled, the PLL is turned off and the differential clock
and V = 2.5V for differential output drivers
DDQ
outputs are 3-stated. When the AV is strapped low, the PLL is
DD
Packages (Pb-free and Green available):
turned off and bypassed for test purposes.
- 48-pin TSSOP
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857B clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CV857B is also able to track Spread Spectrum Clocking for
reduced EMI.
Block Diagram
Pin Configurations: 48-pin TSSOP (package code A)
Y0
Y0
Y1
1 48
GND GND
CLK
2
Y0 47
Y1 Y5
CLK
3 46
Y0 Y5
Y2
PLL
V 4 45
FBIN V
DDQ DDQ
Y2
5 44
Y1 Y6
FBIN
Y3 6 43
Y1
Y6
7 42
GND GND
Y3
8 41
GND GND
Y4
9 40
Y2 Y7
10 39
Y4 Y2
Y7
V 11 38
DDQ V
Y5 DDQ
V 12 37
DDQ PWRDWN
Y5
13 36
CLK FBIN
Y6
14 35
CLK
FBIN
Powerdown
V
15 34
PWRDWN DDQ V
Y6 DDQ
and Test
AV 16 33
FBOUT
DD
AV
DD Y7
Logic
17 32 FBOUT
AGND
Y7 18 31
GND GND
19 30
Y3
Y8 Y8
20 29
Y3
Y8
Y8
V 21 28
V
DDQ
DDQ
Y9
22 27
Y4 Y9
23 26
Y4
Y9 Y9
24 25
GND GND
FBOUT
FBOUT
PS8639B 10/29/03
1PI6CV857B
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012
Pinout Table
P.in NamePein NoIn/O Typ Descriptio
CLK 13
ItReference Clock inpu
CLK 14
Y6x 3,5,10,20,22,27,29,39,44,4 Clock outputs.
Y7x2.,6,9,19,23,26,30,40,43,4 Complement Clock outputs
O
FBOUT 32
Feedback output, and Complement Feedback Output
FBOUT 33
FBIN 36
Feedback Input, and Complement Feedback Input
FBIN 35
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0,
I
the part is powered down and the differential clock outputs are disabled to a
P7WRDWN 3
3-state. When PWRDWN = 1, all differential clock outputs are enabled and run
at the same frequency as CLK.
V 4,11,12,15,21,28,34,38,45 Power Supply for I/O.
DDQ
Analog /core power supply. AV can be used to bypass the PLL for testing
DD
Power
AV 16 purposes. When AV is strapped to ground, PLL is bypassed and CLK is
DD DD
buffered directly to the device outputs.
A7GND 1 Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
G8ND1d,7,8,18,24,25,31,41,42,4 Groun
Function Table
Isnputs OLutput PL
AVPKWRDWNCKL CYL YFTBOUT FBOU
DD
GHND L H L H L H Bypassed/off
GHND H L H L H L Bypassed/off
XL L H Z Z Z Z off
XL H L Z Z Z Z off
2H.5V(nom) L H L H L H on
2H.5V(nom) H L H L H L on
(1)
2X.5V(nom) <20 MHz ZZ Z Z off
Notes: For testing and power saving purposes, PI6CV857B will power down if the frequency of the reference inputs CLK, CLK is
well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857B will
be powered down when the CLK,CLK stop running.
Z = High impedance
X = Dont care
PS8639B 10/29/03
2