PI6CVF857 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features Product Description Operating Frequency up to 220 MHz for PC3200 Registered PI6CVF857 PLL clock device is developed for registered DDR DIMM DIMM applications applications. The device is a zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of Distributes one differential clock input pair to ten differential clock outputs (Y 0:9 , Y 0:9 ), and one differential pair feedback clock clock output pairs outputs (FBOUT,FBOUT) . The clock outputs are controlled by the Inputs (CLK,CLK) and (FBIN,FBIN) input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V Input PWRDWN: LVCMOS LVCMOS input (PWRDWN), and the Analog Power input (AV ). DD When input PWRDWN is low while power is applied, the input Outputs (Yx, Yx), (FBOUT, FBOUT) receivers are disabled, the PLL is turned off, and the differential clock External feedback pins (FBIN,FBIN) are used to outputs are 3-stated. When the AV is strapped low, the PLL is DD synchronize the outputs to the clock input turned off and bypassed for test purposes. Operates at 2.5V for PC1600, PC2100, PC2700, When the input frequency falls below a suggested detection fre- and 2.6V for PC3200 quency that is below the operating frequency of the PLL, the device Packaging (Pb-free & Green available): will enter a low power mode. An input frequency detection circuit will 48-pin TSSOP detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CVF857 clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor- Block Diagram mance, low-skew, low-jitter output differential clocks (Y 0:9 , Y 0:9 ). The PI6CVF857 is also able to track Spread Spectrum Clocking for reduced EMI. Y0 Y0 Y1 CLK Y1 CLK Y2 PLL FBIN Y2 FBIN Y3 Y3 Y4 Y4 Y5 Y5 Y6 Powerdown PWRDWN Y6 and Test AV DD Y7 Logic Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT 08-0298 PS8683D 11/12/08 1PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Configuration TSSOP ( A) Pin Configuration TQFN (ZD) 1 48 GND GND 2 47 Y0 Y5 3 46 Y0 Y5 V 4 45 V DDQ DDQ 5 44 Y1 Y6 6 43 Y1 Y6 7 42 GND GND 40 39 38 37 36 35 34 33 32 31 GND 1 30 Y7 8 41 GND GND Y2 2 29 Y7 9 40 Y2 Y7 Y2 3 28 V DDQ 10 39 Y2 48-Pin Y7 V 4 27 PWRDWN V DDQ 11 38 DDQ V A DDQ V 12 37 CLK 5 26 FBIN DDQ PWRDWN GND 13 36 FBIN CLK 6 25 FBIN CLK 14 35 CLK V 7 24 V FBIN DDQ DDQ V 15 34 DDQ V AV 8 23 V DDQ DD DDQ AV 16 33 DD FBOUT AGND 9 22 FBOUT 17 32 AGND FBOUT GND 10 21 FBOUT 18 31 11 12 13 14 15 16 17 18 19 20 GND GND 19 30 Y3 Y8 20 29 Y3 Y8 V 21 28 DDQ V DDQ 22 27 Y4 Y9 23 26 Y4 Y9 24 25 GND GND 08-0298 PS8683D 10/06/08 2 Y3 Y1 Y3 Y1 V DDQ V DDQ Y4 Y0 Y4 Y0 Y9 Y5 Y9 Y5 V DDQ V DDQ Y8 Y6 Y6 Y8