IREF 16 10 VDD VDD A 17 9 PWRDWN VDD 18 8 PLL/BYPASS SRC 19 7 VDD SRC 20 6 OUT1 PI6PCIEB24 1:4 PCI Express Clock Driver Features Description Phase jitter filter for PCIe 2.0 application Pericom Semiconductor s PI6PCIEB24 is a PCI Express (PCIe) Four pairs of HCSL PCIe 2.0 Differential Clocks 2.0 compliant high-speed, low-noise differential clock buffer. e Th device distributes the input differential PCIe clock to four differ- Prop delay < 250ps (in PLL mode) ential pairs of clock outputs with zero delay PLL. Low skew < 50ps Low jitter < 50ps cycle-to-cycle < 1 ps additive RMS phase jitter 100 MHz PLL Mode operation 3.3V operation Packaging (Pb-free and Green): 20-Pin 4.0mm x 4.0mm x0.75mm TQFN (ZD20) Block Diagram Pin Configuration OE 0 OUT0 OUT0 OUT1 VDD 1 15 OUT3 OUT1 2 OUT0 14 OUT3 SRC OUT2 SRC 3 13 OUT0 OE 3 OUT2 OE 0 4 12 OUT2 OUT3 OUT3 OUT1 5 11 OUT2 OE 3 PWRDWN PLL PLL/BYPASS www.pericom.com PS9070A 09/01/10 10-0210 1PI6PCIEB24 1:4 PCI Express Clock Driver Pin Descriptions Pin Name Type Pin No Description SRC & SRC Input 19, 20 0.7V Differential SRC input from PI6C410 clock synthesizer OUT 0:3 & OUT 0:3 Output 2, 3, 5, 6, 12, 11, 15, 14 0.7V Differential outputs IREF Input 16 External resistor connection to set the differential output current V Power 1, 7, 10, 18 3.3V Power Supply for Outputs DD PWRDWN Input 9 3.3V LVTTL active LOW input for power down operation VDD A Power 17 3.3V Power Supply for PLL PLL/BYPASS Input 8 When HIGH, PLL is enabled, When LOW, PLL is bypassed. OE 0, OE 3 Input 4, 13 When HIGH, enables corresponding OUT0, OUT3 respectively. Ground connection is through the package metal plate underneath. www.pericom.com PS9070A 09/01/10 10-0210 2