PI74SSTVF16857 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 14-Bit Registered Buffer Product Features Product Description PI74 SSTVF16857 is designed for low-voltage operation, Pericom Semiconductors PI74SSTVF16857 series of logic circuits 2.5V for PC1600 ~ PC2700 2.6V for PC3200 are produced using the Companys advanced sub-micron CMOS Supports SSTL 2 Class I output specifications technology, achieving industry leading speed. SSTL 2 Input and Output Levels The 14-bit PI74SSTVF16857 universal bus driver is designed Designed for DDR Memory for 2.5V to 2.6V V operation and SSTL 2 I/O Levels except for DD Flow-Through Architecture the RESET input which is LVCMOS. Packaging Options (Pb-free available): Data flow from D to Q is controlled by the differential clock , CLK, 48-pin 240 mil wide plastic TSSOP (A) CLK and RESET. Data is triggered on the positive edge of CLK. 48-pin 173 mil wide plastic TVSOP (K) CLK must be used to maintain noise margins. Logic Block Diagram RESET must be supported with LVCMOS levels as V may not REF be stable during power-up. RESET is asynchronous and is intended 38 CLK 39 for power-up only and when low assures that all of the registers reset CLK to the Low State, Q outputs are low, and all input receivers, data and 34 RESET R clock, are switched off. 1 CLK Q1 48 Pericoms PI74SSTVF16857 is characterized for operation from D1 D 35 0 to 70C. V REF Product Pin Configuration TO 13 OTHER CHANNELS Q1 1 48 D1 Product Pin Description Q2 2 47 D2 Pin Name Description GND 3 46 GND RESET Reset (Active Low) V 4 45 V DDQ DD CLK Clock Input Q3 5 44 D3 CLK Clock Input Q4 6 43 D4 D Data Input Q5 7 42 D5 Q Data Output GND 8 41 D6 GND Ground V 9 40 D7 DDQ 48-Pin V Core Supply Voltage Q6 10 39 DD CLK A, K Q7 11 38 V Output Supply Voltage CLK DDQ V 12 37 V V Input Reference Voltage DDQ REF DD GND 13 36 GND (1) Truth Table Q8 14 35 V REF Isnputs Output Q9 15 34 RESET RKESETCKL CDL Q V 16 33 D8 DDQ GND 17 32 LX X X L D9 Q10 18 31 D10 H HH Q11 19 30 D11 LL Q12 20 29 D12 (2) HHLHor LXor Qo V 21 28 V DDQ DD Notes: GND 22 27 GND 2. Output level before the 1. H = High Signal Level indicated steady state Q13 23 26 D13 L = Low Signal Level input conditions were = Transition LOW-to-HIGH Q14 24 25 D14 established. = Transition HIGH-to-LOW X = Irrelevant PS8656A 05/27/03 1 VPI74SSTVF16857 14-Bit Registered Buffer 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Plarameter Ssymbo Rsating Unit o Sgtorage Temperature T0st 65 to 15 C SVupply Voltage or V 0.5 to 3.6 DD DDQ (1) Input Voltage V 0.5 to V + 0.5 V I DD (1,2) Output Voltage V 0.5 to V + 0.5 O DDQ IInput Clamp Current V00 5 I K, I < OIutput Clamp Current V005 O K, O < mA CIontinuous Output Current V 0 to V 50 O, O = DDQ V , V,Ior GND current/pin Io0r GND 10 DD DDQ DD, DDQ A-Package 70 o Package Thermal Impedance J C/W A K8-Package 5 Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V > V . O DDQ 3. The package thermal impedance is calculated in accordance with JESD 51-7. PS8656A 05/27/03 2