54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop LOW input to C sets Q to LOW level D General Description Clear and Set are independent of clock The F109 consists of two high-speed, completely indepen- Simultaneous LOW on C and S makes both Q and Q dent transition clocked JK flip-flops. The clocking operation D D is independent of rise and fall times of the clock waveform. HIGH TheJKdesignallowsoperationasaDflip-flop(refertoF74 data sheet) by connecting the J and K inputs. Features Asynchronous Inputs: n Guaranteed 4000V minimum ESD protection. LOW input to S sets Q to HIGH level D OrderingCode: See Section 0 DSXXX Commercial Military Package Package Description Number 74F109PC N16E 16-Lead (0.300 Wide) Molded Dual-in-Line 54F109DM (Note 2) J16A 16-Lead Ceramic Dual-in-Line 74F109SC (Note 1) M16A 16-Lead (0.150 Wide) Molded Small Outline, JEDEC 74F109SJ (Note 1) M16D 16-Lead (0.300 Wide) Molded Small Outline, EIAJ 54F109FM (Note 2) W16A 16-Lead Cerpack 54F109LM (Note 2) E20A 16-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 reel. Use suffix = SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC DS009471-3 DS009471-4 DS009471-6 FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation. 1997 National Semiconductor Corporation DS009471 www.national.com 1 PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof 1Connection Diagrams Pin Assignment Pin Assignment for DIP, SOIC and Flatpak for LCC DS009471-1 DS009471-2 Unit Loading/Fan Out See Section 0 for U.L. definitions DSXXX 54F/74F Pin Names Description U.L. Input I /I IH IL HIGH/LOW Output I /I OH OL J,J,K,K Data Inputs 1.0/1.0 20 A/0.6 mA 1 2 1 2 CP,CP Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 A/0.6 mA 1 2 C ,C Direct Clear Inputs (Active LOW) 1.0/3.0 20 A/1.8 mA D1 D2 S ,S Direct Set Inputs (Active LOW) 1.0/3.0 20 A/1.8 mA D1 D2 Q,Q,Q,Q Outputs 50/33.3 1 mA/20 mA 1 2 1 2 Truth Table Inputs Outputs S C CP J K QQ D D LH X X X H L HL X X X L H LL X X X H H N HH ll L H N HH h l Toggle N HH lh Q Q 0 0 N HH hh H L HH L X X Q Q 0 0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q (Q ) = Before LOW-to-HIGH Transition of Clock 0 0 Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. www.national.com 2 PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof 2