MC74ACT273DWG ON Semiconductor

MC74AC273, MC74ACT273 Octal D Flip-Flop The MC74AC273/74ACT273 has eight edge-triggered Dtype flipflops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flipflops simultaneously. The register is fully edge-triggered. The state of each D input, one www.onsemi.com setup time before the LOWtoHIGH clock transition, is transferred to the corresponding flipflops Q output. All outputs will be forced LOW independently of Clock or Data SOIC20WB inputs by a LOW voltage level on the MR input. The device is useful 20 SUFFIX DW for applications where the true output only is required and the Clock CASE 751D and Master Reset are common to all storage elements. 1 Features Ideal Buffer for MOS Microprocessor or Memory TSSOP20 20 Eight Edge-Triggered D FlipFlops SUFFIX DT CASE 948E Buffered Common Clock Buffered, Asynchronous Master Reset 1 See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version PIN ASSIGNMENT See MC74AC374 for 3-State Version PIN FUNCTION Outputs Source/Sink 24 mA D D Data Inputs 0 7 ACT273 Has TTL Compatible Inputs MR Master Reset These are PbFree Devices CP Clock Pulse Input Q Q Data Outputs 0 7 V Q D D Q Q D D Q CP CC 7 7 6 6 5 5 4 4 20 19 18 17 16 15 14 13 12 11 D D D D D D D D 0 1 2 3 4 5 6 7 CP MR Q Q Q Q Q Q Q Q 0 1 2 3 4 5 6 7 1 2 3456 7 8 9 10 MR Q D D Q Q D D Q GND Logic Symbol 0 0 1 1 2 2 3 3 (Top View) Pinout: 20Lead Packages Conductors ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. MODE SELECT-FUNCTION TABLE Inputs Outputs Operating Mode MR CP D Q n n DEVICE MARKING INFORMATION See general marking information in the device marking Reset (Clear) L X X L section on page 6 of this data sheet. Load 1 H H H Load 0 H L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: December, 2016 Rev. 8 MC74AC273/DMC74AC273, MC74ACT273 D D D D D D D D 0 1 2 3 4 5 6 7 CP DQ DQ DQ DQ DQ DQ DQ DQ CP CP CP CP CP CP CP CP R R R R R R R R D D D D D D D D MR O O O O O O O O 0 1 2 3 4 5 6 7 NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1. Logic Diagram www.onsemi.com 2