54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins May 1995 54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features Y Common parallel I/O for reduced pin count The F299 is an 8-bit universal shift/storage register with Y TRI-STATE outputs. Four modes of operation are possi- Additional serial inputs and outputs for expansion ble: hold (store), shift left, shift right and load data. The par- Y Four operating modes: shift left, shift right, load and allel load inputs and flip-flop outputs are multiplexed to re- store duce the total number of package pins. Additional outputs, Y TRI-STATE outputs for bus-oriented applications Q Q , are provided to allow easy serial cascading. A sep- 0 7 Y Guaranteed 4000V minimum ESD protection arate active LOW Master Reset is used to reset the register. Package Commercial Military Package Description Number 74F299PC N20A 20-Lead (0.300 Wide) Molded Dual-In-Line 54F299DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line 74F299SC (Note 1) M20B 20-Lead (0.300 Wide) Molded Small Outline, JEDEC 74F299SJ (Note 1) M20D 20-Lead (0.300 Wide) Molded Small Outline, EIAJ 54F299FM (Note 2) W20A 20-Lead Cerpack 54F299LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/95151 TL/F/95154 TRI-STATE is a registered trademark of National Semiconductor Corporation. C 1995 National Semiconductor Corporation TL/F/9515 RRD-B30M75/Printed in U. S. A.Connection Diagrams Pin Assignment Pin Assignment for DIP, SOIC and Flatpak for LCC TL/F/95153 TL/F/95152 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I /I IH IL HIGH/LOW Output I /I OH OL b CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/ 0.6 mA b DS Serial Data Input for Right Shift 1.0/1.0 20 mA/ 0.6 mA 0 b DS Serial Data Input for Left Shift 1.0/1.0 20 mA/ 0.6 mA 7 b S ,S Mode Select Inputs 1.0/2.0 20 mA/ 1.2 mA 0 1 b MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/ 0.6 mA b OE ,OE TRI-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 mA/ 0.6 mA 1 2 b I/O I/O Parallel Data Inputs or 3.5/1.083 70 mA/ 0.65 mA 0 7 b TRI-STATE Parallel Outputs 150/40(33.3) 3 mA/24 mA (20 mA) b Q ,Q Serial Outputs 50/33.3 1 mA/20 mA 0 7 Functional Description The F299 contains eight edge-triggered D-type flip-flops A HIGH signal on either OE or OE disables the TRI- 1 2 and the interstage logic necessary to perform synchronous STATE buffers and puts the I/O pins in the high impedance shift left, shift right, parallel load and hold operations. The state. In this condition the shift, hold, load and reset opera- type of operation is determined by S and S , as shown in tions can still occur. The TRI-STATE outputs are also dis- 0 1 the Mode Select Table. All flip-flop outputs are brought out abled by HIGH signals on both S and S in preparation for 0 1 through TRI-STATE buffers to separate I/O pins that also a parallel load operation. serve as data inputs in the parallel load mode. Q and Q 0 7 Mode Select Table are also brought out on other pins for expansion in serial shifting of longer words. Inputs Response A LOW signal on MR overrides the Select and CP inputs MR S S CP 1 0 and resets the flip-flops. All other state changes are initiated e L X X X Asynchronous Reset Q Q LOW by the rising edge of the clock. Inputs can change when the 0 7 clock is in either state provided only that the recommended HH HL Parallel Load I/O x Q n n setup and hold times, relative to the rising edge of CP, are HL HL Shift Right DS x Q ,Q xQ , etc. 0 0 0 1 observed. HH L L Shift Left DS x Q ,Q xQ , etc. 7 7 7 6 H L L X Hold e H HIGH Voltage Level e L LOW Voltage Level e X Immaterial e L LOW-to-HIGH Clock Transition 2