54F379DMQB E2v

54F/74F379 Quad Parallel Register with Enable August 1995 54F/74F379 Quad Parallel Register with Enable General Description Features Y Edge triggered D-type inputs The F379 is a 4-bit register with buffered common Enable. Y This device is similar to the F175 but features the common Buffered positive edge-triggered clock Enable rather than common Master Reset. Y Buffered common enable input Y True and complement outputs Y Guaranteed 4000V minimum ESD protection Package Commercial Military Package Description Number 74F379PC N16E 16-Lead (0.300 Wide) Molded Dual-In-Line 54F379DM (QB) J16A 16-Lead Ceramic Dual-In-Line 74F379SC (Note 1) M16A 16-Lead (0.300 Wide) Molded Small Outline, JEDEC 74F379SJ (Note 1) M16D 16-Lead (0.300 Wide) Molded Small Outline, EIAJ 54F379FM (QB) W16A 16-Lead Cerpack 54F379LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C e Note 1: Devices also available in 13 reel. Use suffix SCX and SJX. Logic Symbols Connection Diagrams Pin Assignment Pin Assignment IEEE/IEC DIP, SOIC and Flatpak for LCC TL/F/95271 TL/F/95272 TL/F/95275 TL/F/95273 TRI-STATE is a registered trademark of National Semiconductor Corporation. C 1995 National Semiconductor Corporation TL/F/9527 RRD-B30M115/Printed in U. S. A.Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I /I IH IL HIGH/LOW Output I /I OH OL b E Enable Input (Active LOW) 1.0/1.0 20 mA/ 0.6 mA D D Data Inputs 1.0/1.0 20 mA/b0.6 mA 0 3 b CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/ 0.6 mA b Q Q Flip-Flop Outputs 50/33.3 1 mA/20 mA 0 3 b Q Q Complement Outputs 50/33.3 1 mA/20 mA 0 3 Functional Description Truth Table The F379 consists of four edge-triggered D-Type flip-flops Inputs Outputs with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. E CP D Q Q n n n When the E is input HIGH, the register will retain the present H L XNC NC data independent of the CP input. The D and E inputs can n L L HH L change when the clock is in either state, provided that the L L LL H recommended setup and hold times are observed. e H HIGH Voltage Level e L LOW Voltage Level e X Immaterial e L LOW-to-HIGH Transition e NC No Change Logic Diagram TL/F/95274 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2