INCH-POUND MIL-M-38510/2G 8 February 2005 SUPERSEDING MIL-M-38510/2E 24 December 1974 MIL-M-0038510/2F (USAF) 24 OCTOBER 1975 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, TTL, FLIP-FLOPS, MONOLITHIC SILICON Inactive for new design after 7 September 1995 This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, TTL, bistable logic microcircuits. Three product assurance classes and a choice of case outlines/lead finish are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type Circuit 01 Single J-K master-slave flip-flop 02 Dual J-K master-slave flip-flop, no preset 03 Dual J-K master-slave flip-flop, no preset 04 Dual J-K master-slave flip-flop 05 Dual D-type edge-triggered flip-flop 06 Single edge-triggered J-K flip-flop 07 Dual D-type edge-triggered flip-flop, buffered output 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to bipolar dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at MIL-M-38510/2G 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A GDFP5-F14 or CDFP6-F14 14 Flat pack B GDFP4-F14 14 Flat pack C GDIP1-T14 or CDIP2-T14 14 Dual-in-line D GDFP1-F14 or CDFP2-F14 14 Flat pack E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack 1.3 Absolute maximum ratings. Supply voltage range ............................................................................. -0.5 V dc to +7.0 V dc Input voltage range ................................................................................ -1.5 V dc at -12 mA to 5.5 V dc Storage temperature range .................................................................... -65 to +150C Maximum power dissipation, (P ) D flip-flop, 1/....................................................................................... 110 mW 1/ Lead temperature (soldering, 10 seconds).............................................. 300C Thermal resistance, junction to case ( ):.............................................. 0.09C/mW for flat packs JC 0.08C/mW for dual-in-line pack Junction temperature (T )........................................................................ 175C J 1.4 Recommended operating conditions. Supply voltage (V ) .............................................................................. 4.5 V dc minimum to CC 5.5 V dc maximum Minimum high-level input voltage (V ) ................................................... 2.0 V dc IH Maximum low-level input voltage (V ) .................................................... 0.8 V dc IL Normalized fanout (each output) 2/....................................................... 10 maximum Case operating temperature range (T ) .................................................. -55 C to +125 C C Input set up time: Device type 01, 02, 03 and 04, ......................................................... clock pulse width Device type 05, 06, and 07................................................................ 20 ns Input hold time Device types 01, 02, 03 and 04......................................................... 0 ns Device type 05, 06 and 07 ................................................................ 5 ns 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 1/ Must withstand the added P due to short circuit condition (e.g. I ) at one output for 5 seconds D OS duration 2/ Device will fanout in both high and low levels to the specified number of I /I inputs of the same device type IL1 IH1 as that being tested. 2