FUJITSU SEMICONDUCTOR FACT SHEET NP501-00021-2v0-E FRAM MB85RC128A 2 MB85RC128A is a 128K-bits FRAM LSI with serial interface (I C), using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. FEATURES Bit configuration 16,384 words 8 bits Two-wire serial interface Fully controllable by two ports: serial clock (SCL) and serial data (SDA). Operating frequency 1 MHz (Max.) 12 Read/write endurance 10 times / byte Data retention 10 years (+85), 95 years (+55), over 200 years (+35) Operating power supply voltage 2.7 to 3.6V Low power consumption Operating current 250A (Typ1MHz), Standby current 5A (Typ.) Operating temperature range -40 to +85 Package 8-pin plastic SOP (FPT-8P-M02) RoHS compliant ORDERING INFORMATION Product name Package Shipping form 8-pin plastic SOP MB85RC128APNF-G-JNE1 (FPT-8P-M02) Tube 3.90mm5.05mm,1.27mm pitch 8-pin plastic SOP MB85RC128APNF-G-JNERE1 (FPT-8P-M02) Embossed Carrier tape 3.90mm5.05mm,1.27mm pitch PACKAGE EXAMPLE OF REFERENCE 8-pin plastic SOP (FPT-8P-M02) 2013.5 1/2 Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85RC128A PIN ASSIGNMENT (TOP VIEW) Pin No. Pin name Description Device Address pins A0 1 8 VDD MB85RC64 can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD 1 to 3 A0 to A2 pin or VSS pin externally. Only if the combination of VDD and VSS pin matches a Device Address Code inputted from the SDA pin, the device operates. In the 2 7 A1 WP open pin state, A0, A1, and A2 are internally pulled-down and recognized as the level. 4 VSS Ground pin 3 6 SCL A2 Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory 5 SDA address and writing/reading data. It is possible to connect multiple devices. VSS 4 5 SDA It is an open drain output, so a pull-up resistor is required to be connected to the external circuit. Serial Clock pin 6 SCL This is a clock input pin for input/output serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When Write Protect pin is the level, writing operation is disabled. When Write Protect pin is the level, the entire memory region can be overwritten. 7 WP Reading operation is always enabled regardless of Write Protect pin input level. The Write Protect pin is internally pulled down to VSS pin, and that is recognized as the level (write enabled) when the pin is the open state. Supply Voltage pin 8 VDD BLOCK DIAGRAM Serial/Parallel Converter SDA FRAM Array 16,384 8 SCL WP Column Decoder/Sense Amp./ Write Amp. A0, A1, A2 2 I C The MB85RC128A has the two-wire serial interface the I2C bus, and operates as a slave device. The I2C bus defines communication roles of master and slave devices, with the master side holding the authority to initiate control. Furthermore, an I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. NP501-00021-2v0-E 2013.5 2/2 Copyright2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved Control Logic Address Counter Row Decoder