FUJITSU SEMICONDUCTOR DS051311011E DATA SHEET Memory FRAM 2 128 K (16 K 8) Bit I C MB85RC128 DESCRIPTION The MB85RC128 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, the MB85RC128 is able to retain data without using a data backup battery. The read/write endurance of the nonvolatile memory cells used for the MB85RC128 has improved to be at 12 2 least 10 cycles, significantly outperforming Flash memory and E PROM in the number. The MB85RC128 does not need a polling sequence after writing to the memory such as the case of Flash 2 memory or E PROM. FEATURES Bit configuration : 16,384 words 8 bits Two-wire serial interface : Fully controllable by two ports: serial clock (SCL) and serial data (SDA). Operating frequency : 400 kHz (Max) 12 Read/write endurance : 10 times / byte Data retention : 10 years ( + 85 C), 95 years ( + 55 C), over 200 years ( + 35 C) Operating power supply voltage : 2.7 V to 3.6 V Low power consumption : Operating power supply current 100 A (Typ 400 kHz) Standby current 5 A (Typ) Operation ambient temperature range : 40 C to + 85 C Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright 2010-2015 FUJITSU SEMICONDUCTOR LIMITED 2015.5MB85RC128 PIN ASSIGNMENT (TOP VIEW) A0 1 8 VDD 2 7 A1 WP A2 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin Pin Name Functional Description Number Device Address pins The MB85RC128 can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect 1 to 3 A0 to A2 these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches a Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A0, A1 and A2 pins are internally pulled- down and recognized as the L level. 4 VSS Ground pin Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory 5SDA address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the ex- ternal circuit. Serial Clock pin 6SCL This is a clock input pin for input/output serial data. Data is sampled on the ris- ing edge of the clock and output on the falling edge. Write Protect pin When the Write Protect pin is the H level, the writing operation is disabled. When the Write Protect pin is the L level, the entire memory region can be 7WP overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The Write Protect pin is internally pulled down to VSS pin, and that is recognized as the L level (write enabled) when the pin is the open state. 8 VDD Supply Voltage pin 2 DS051311011E