FUJITSU SEMICONDUCTOR DATA SHEET DS501-00008-1v0-E Memory FRAM 128K (16 K 8) Bit SPI MB85RS128A DESCRIPTION MB85RS128A is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS128A adopts the Serial Peripheral Interface (SPI). The MB85RS128A is able to retain data without using a back-up battery, as is needed for SRAM. 10 The memory cells used in the MB85RS128A can be used for 10 read/write operations, which is a significant 2 improvement over the number of read and write operations supported by Flash memory and E PROM. 2 MB85RS128A does not take long time to write data unlike Flash memories nor E PROM, and MB85RS128A takes no wait time. FEATURES Bit configuration : 16,384 words 8 bits Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : 25 MHz (Max) 10 Read/write endurance : 10 times/bit Data retention : 10 years (+55 C) Operating power supply voltage : 3.0 V to 3.6 V Low power consumption : Operating po wer supply current 5 mA (Typ 25 MHz) Standby current 9 A (Typ) Operating temperature range : 40 C to + 85 C Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.10MB85RS128A PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD 2 7 SO HOLD WP 3 6 SCK GNDS4 5I (FPT-8P-M02) PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chips select. When CS is the H level, device is in deselect 1CS (standby) status as long as device is not write status internally, and SO becomes High- Z. Inputs from other pins are ignored at this time. When CS is the L level, device is in select (active) status. CS has to be the L level before inputting op-code. Write Protect pin 3WP This is a pin to control writing to a status register. When WP is the L level, writing to a status register is not operated. Hold pin This pin is used to interrupt serial input/output without making chips deselect. When 7HOLD HOLD is the L level, hold operation is activated, SO becomes High-Z, SCK and SI be- come dont care. While the hold operation, CS has to be retained the L level. Serial Clock pin 6SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin 2 DS501-00008-1v0-E