FUJITSU SEMICONDUCTOR DS07-13731-3E DATA SHEET 16-bit Proprietary Microcontroller CMOS 2 F MC-16LX MB90895 Series MB90F897/F897S/MB90V495G nnnn DESCRIPTION MB90895 series devices are 16-bit micro general-purpose controllers designed for applications which need high- speed real-time processing. The devices of this series are high-performance 16-bit CPU micro controllers em- ploying of the dual operation flash memory and CAN controller on LQFP-48 small package. 2 The system, inheriting the architecture of F MC* family, employs additional instruction ready for high-level lan- guages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instruc- tions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits). The peripheral resources of MB90895 series include the following: 8/10-bit A/D converter, UART0/UART1 (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU)), and CAN controller. 2 *: F MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd. nnnn FEATURES Models that support +125 C Clock Built-in PLL clock frequency multiplication circuit Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). Operation by sub-clock (8.192 kHz) is allowed. (MB90F897) Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multi- plied PLL clock). 16 Mbyte CPU memory space 24-bit internal addressing (Continued) nnnn PACKAGE 48-pin plastic, LQFP (FPT-48P-M26) MB90895 Series (Continued) Instruction system best suited to controller Wide choice of data types (bit, byte, word, and long word) Wide choice of addressing modes (23 types) Enhanced multiply-divide instructions and RETI instructions Enhanced high-precision computing with 32-bit accumulator Instruction system compatible with high-level language (C language) and multitask Employing system stack pointer Enhanced various pointer indirect instructions Barrel shift instructions Increased processing speed 4-byte instruction queue Powerful interrupt function with 8 levels and 34 factors Automatic data transfer function independent of CPU 2 Expanded intelligent I/O service function (EI OS): Maximum of 16 channels Low power consumption (standby) mode Sleep mode (a mode that halts CPU operating clock) Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only) Clock mode (a mode that operates sub clock and clock timer only) Stop mode (a mode that stops oscillation clock and sub clock) CPU blocking operation mode Process CMOS technology I/O port General-purpose input/output port (CMOS output) : MB90F897 : 34 ports (including 4 high-current output ports) MB90F897S : 36 ports (including 4 high-current output ports) Timer Time-base timer, clock timer, watchdog timer: 1 channel 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels 16-bit reload timer: 2 channels 16-bit input/output timer - 16-bit free run timer: 1 channel - 16-bit input capture: (ICU): 4 channels Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin input. CAN controller: 1 channel Compliant with Ver 2.0A and Ver 2.0B CAN specifications 8 built-in message buffers Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock) CAN wake-up UART0 (SCI), UART1(SCI): 2 channel Equipped with full-duplex double buffer Clock-asynchronous or clock-synchronous serial transmission is available. DTP/External interrupt: 4 channels, CAN wake-up: 1channel 2 Module for activation of expanded intelligent I/O service (EI OS), and generation of external interrupt. Delay interrupt generator module Generates interrupt request for task switching. 8/10-bit A/D converter: 8 channels Resolution is selectable between 8-bit and 10-bit. Activation by external trigger input is allowed. Conversion time: 6.125 m s (at 16-MHz machine clock, including sampling time) Program patch function Address matching detection for 2 address pointers. 2