Double Pulse Switching Board GA100SBJT12-FR4
Double Pulse Switching Board
V = 1200 V
DS, MAX
I = 100 A
D, MAX
Features Compatible
1200 V, 100 A Testing SiC Junction Transistors (SJT)
Low Series Inductance Design SiC MOSFETS
Wide, 6 oz. Copper Current Traces Silicon Power MOSFETs
Multiple DUT and FWD Connections for Durability Fast Silicon IGBTs
Low Resistance and Inductance Gate Drive Connection
Electrical Characteristics
Parameter Symbol Conditions Value Unit Notes
Test Voltage Maximum V 1200 V
DS, MAX
Drain Current Maximum I 100 A
D, MAX
Capacitor Bank C 5.0 F
bank
V = 800 V, I = 6 A
Parasitic Inductance L DS D 60 nH
s
Maximum Stored Energy E V = 1200 V 3.6 J
max DS
Overview
The GeneSiC Double Pulse Test Board is designed for performing
switching tests on a wide variety of silicon and SiC power transistors. It
is designed using low ESL capacitors and PCB traces to have a low
parasitic series inductance (L ) current path. This allows recorded data
S
to be most representative of the device under test (DUT) and minimize
testing circuit distortions. The board is capable of up to 1200 V and
100 A. User-provided external load inductor, DUT, and free-wheeling
diode (FWD) may be soldered directly to the board, without testing
sockets, for the lowest possible contact resistance and inductance. A
gate drive circuit board may be mounted directly on to the Test Board
for a short, low inductance path to the DUT gate pin connection.
Figure 1: Double Pulse Test Board
Figure 2: GeneSiC Semiconductor Switching Test Board Schematic
Sept. 2015
Double Pulse Switching Board GA100SBJT12-FR4
MHV Voltage Conn.
Voltage Balancing
5 F Capacitor Bank
+
Drain Current
External
FWD
Sensor Conn.
Load Inductor
Connection
Gate Drive
DUT
Conn.
Figure 3: Switching Test Board with Labeling
MHV Voltage Connection
High voltage for testing up to 1200 V is supplied to the Test Board through a MHV coaxial connection. Voltage may be generated through a
high voltage power supply.
Capacitor Bank
The capacitor bank is comprised of 20, 1 F, 630 V capacitors to store up to 3.6 J of energy to supply to the DUT. The bank includes 10 low
effective series inductance (ESL) surface mount ceramic capacitors to allow DUT drain currents to rise and fall with minimal circuit
interference. Copper traces of 6 oz. thickness on the Test Board also minimize parasitic inductance.
Voltage Balancing Network
A voltage balancing network of two 1 M , 2 W SMD resistors is used to ensure an equal potential is across the series connected capacitors
on the Test Board along with two blocking rectifiers to protect against extreme overvoltage of the energy storage capacitors.
External Load Inductor
A load inductor (not provided) can be soldered directed to the HV and Drain nodes on their provided connection pads. Care should be taken to
ensure the voltage rating of the inductor is not exceeded. Also, if the chosen inductor value is too large the capacitor bank may discharge
before the inductor is fully charged to the desired test current I level during double pulse testing. An inductance of L 1.0 mH is suggested.
D load
Device Under Test (DUT) and Free Wheeling Diode (FWD)
The DUT and FWD should be soldered into the connection terminals with minimal extra lead length. Leads extending through the Test Board
should be trimmed from the package to reduce electrical noise which may distort measurement during ultra-fast, high-voltage switching.
Devices may be connected to isolated hotplates while connected to the Test Board for high-temperature testing as desired. It is also
recommended to probe any device voltages (i.e. V , V ) as close as possible to the device for accurate measurement and minimal testing
GS DS
induced voltage and current ringing.
Sept. 2015