1 Mbit (128K x8) Page-Write EEPROM GLS29EE010 GLS29EE0101Mb (x8) Page-Write, Small-Sector flash memories Data Sheet FEATURES: Single Voltage Read and Write Operations Latched Address and Data 4.5-5.5V for GLS29EE010 Automatic Write Timing Superior Reliability Internal V Generation PP Endurance: 100,000 Cycles (typical) End of Write Detection Greater than 100 years Data Retention Toggle Bit Low Power Consumption Data Polling Active Current: 20 mA (typical) for 5V and Hardware and Software Data Protection 10 mA (typical) for 2.7V Product Identification can be accessed via Standby Current: 10 A (typical) Software Operation Fast Page-Write Operation TTL I/O Compatibility 128 Bytes per Page, 1024 Pages JEDEC Standard Page-Write Cycle: 5 ms (typical) Flash EEPROM Pinouts and command sets Complete Memory Rewrite: 5 sec (typical) Packages Available Effective Byte-Write Cycle Time: 39 s (typical) 32-lead PLCC Fast Read Access Time 32-lead TSOP (8mm x 14mm, 8mm x 20mm) 4.5-5.5V operation: 70 and 90 ns 32-pin PDIP 2.7-3.6V operation: 150 and 200 ns All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The GLS29EE010 is a 128K x8 CMOS Page-Write sumption. The GLS29EE010 improves flexibility while EEPROMs manufactured with high-performance Super- lowering the cost for program, data, and configuration Flash technology. The split-gate cell design and thick-oxide storage applications. tunneling injector attain better reliability and manufacturabil- To meet high density, surface mount requirements, the ity compared with alternate approaches. The GLS29EE010 is offered in 32-lead PLCC and 32-lead GLS29EE010 write with a single power supply. Internal TSOP packages. A 600-mil, 32-pin PDIP package is also Erase/Program is transparent to the user. The available. See Figures 2, 3, and 4 for pin assignments. GLS29EE010 conform to JEDEC standard pinouts for byte-wide memories. Device Operation Featuring high performance Page-Write, the GLS29EE010 The Greenliant Page-Write EEPROM offers in-circuit elec- provides a typical Byte-Write time of 39 sec. The entire trical write capability. The GLS29EE010 does not require memory, i.e., 128 Kbyte, can be written page-by-page in as separate Erase and Program operations. The internally little as 5 seconds, when using interface features such as timed Write cycle executes both erase and program trans- Toggle Bit or Data Polling to indicate the completion of a parently to the user. The GLS29EE010 has industry stan- Write cycle. To protect against inadvertent write, the dard optional Software Data Protection, which Greenliant GLS29EE010 has on-chip hardware and Software Data recommends always to be enabled. The GLS29EE010 is Protection schemes. Designed, manufactured, and tested compatible with industry standard EEPROM pinouts and for a wide spectrum of applications, the GLS29EE010 is functionality. offered with a guaranteed Page-Write endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The GLS29EE010 is suited for applications that require convenient and economical updating of pro- gram, configuration, or data memory. For all system applications, the GLS29EE010 significantly improves performance and reliability, while lowering power con- 2010 Greenliant Systems, Ltd. www.greenliant.com S71061-15-00105/101 Mbit Page-Write EEPROM GLS29EE010 Data Sheet The Write operation has three functional cycles: the Soft- Read ware Data Protection load sequence, the page-load cycle, The Read operations of the GLS29EE010 is controlled by and the internal Write cycle. The Software Data Protection CE and OE , both have to be low for the system to obtain consists of a specific three-byte load sequence that allows data from the outputs. CE is used for device selection. writing to the selected page and will leave the When CE is high, the chip is deselected and only standby GLS29EE010 protected at the end of the Page-Write. The power is consumed. OE is the output control and is used page-load cycle consists of loading 1 to 128 bytes of data to gate data from the output pins. The data bus is in high into the page buffer. The internal Write cycle consists of the impedance state when either CE or OE is high. Refer to T time-out and the write timer operation. During the BLCO the Read cycle timing diagram for further details (Figure 5). Write operation, the only valid reads are Data Polling and Toggle Bit. Write The Page-Write operation allows the loading of up to 128 The Page-Write to the GLS29EE010 should always use bytes of data into the page buffer of the GLS29EE010 the JEDEC Standard Software Data Protection (SDP) before the initiation of the internal Write cycle. During the three-byte command sequence. The GLS29EE010 con- internal Write cycle, all the data in the page buffer is written tains the optional JEDEC approved Software Data Protec- simultaneously into the memory array. Hence, the Page- tion scheme. Greenliant recommends that SDP always be Write feature of GLS29EE010 allows the entire memory to enabled, thus, the description of the Write operations will be written in as little as 5 seconds. During the internal Write be given using the SDP enabled format. The three-byte cycle, the host is free to perform additional tasks, such as SDP Enable and SDP Write commands are identical to fetch data from other locations in the system to set up therefore, any time a SDP Write command is issued, the write to the next page. In each Page-Write operation, all Software Data Protection is automatically assured. The the bytes that are loaded into the page buffer must have first time the three-byte SDP command is given, the device the same page address, i.e. A through A . Any byte not 7 16 becomes SDP enabled. Subsequent issuance of the same loaded with user data will be written to FFH. command bypasses the data protection for the page being See Figures 6 and 7 for the Page-Write cycle timing dia- written. At the end of the desired Page-Write, the entire grams. If after the completion of the three-byte SDP load device remains protected. For additional descriptions, sequence or the initial byte-load cycle, the host loads a please see the application notes, The Proper Use of second byte into the page buffer within a byte-load cycle JEDEC Standard Software Data Protection and Protecting time (T ) of 100 s, the GLS29EE010 will stay in the BLC Against Unintentional Writes When Using Single Power page-load cycle. Additional bytes are then loaded consecu- Supply Flash Memories. tively. The page-load cycle will be terminated if no addi- The Write operation consists of three steps. Step 1 is the tional byte is loaded into the page buffer within 200 s three-byte load sequence for Software Data Protection. (T ) from the last byte-load cycle, i.e., no subsequent BLCO Step 2 is the byte-load cycle to a page buffer of the WE or CE high-to-low transition after the last rising edge GLS29EE010. Steps 1 and 2 use the same timing for both of WE or CE . Data in the page buffer can be changed by operations. Step 3 is an internally controlled Write cycle for a subsequent byte-load cycle. The page-load period can writing the data loaded in the page buffer into the memory continue indefinitely, as long as the host continues to load array for nonvolatile storage. During both the SDP three- the device within the byte-load cycle time of 100 s. The byte load sequence and the byte-load cycle, the addresses page to be loaded is determined by the page address of are latched by the falling edge of either CE or WE , the last byte loaded. whichever occurs last. The data is latched by the rising edge of either CE or WE , whichever occurs first. The Software Chip-Erase internal Write cycle is initiated by the T timer after the BLCO rising edge of WE or CE , whichever occurs first. The The GLS29EE010 provides a Chip-Erase operation, which Write cycle, once initiated, will continue to completion, typi- allows the user to simultaneously clear the entire memory cally within 5 ms. See Figures 6 and 7 for WE and CE array to the 1 state. This is useful when the entire device controlled Page-Write cycle timing diagrams and Figures must be quickly erased. 16 and 18 for flowcharts. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the 2010 Greenliant Systems, Ltd. S71061-15-001 05/10 2