GLS29EE512 Small-Sector Flash 512 Kbit (64K x8) Page-Write EEPROM Datasheet 11.000 July 2018 Features Single Voltage Read and Write Operations Automatic Write Timing - 4.5-5.5V for GLS29EE512 - Internal V Generation PP Superior Reliability End of Write Detection - Endurance: 100,000 Cycles (typical) - Toggle Bit - Greater than 100 years Data Retention - Data Polling Low Power Consumption Hardware and Software Data Protection - Active Current: 20 mA (typical) Product Identification can be accessed via - Standby Current: 10 A (typical) Software Operation Fast Page-Write Operation TLL I/O Compatibility - 128 Bytes per Page, 512 Pages JEDEC Standard - Page-Write Cycle: 5 ms (typical) - Flash EEPROM Pinouts and Command Sets - Complete Memory Rewrite: 2.5 sec (typical) Packages Available - Effective Byte-Write Cycle Time: 39 S (typical) - 32-lead PLCC Fast Read Access Time - 32-lead TSOP (8mm x 20mm) - 4.5-5.5V operation: 70 ns All Devices are RoHS Compliant Latched Address and Data Product Description GLS29EE512 Small-Sector Flash is a 64K x8 GLS29EE512 is suited for applications that require CMOS, Page-Write EEPROM manufactured with high- convenient and economical updating of program, performance SuperFlash technology. The split-gate configuration, or data memory. For all system cell design and thick-oxide tunneling injector attain applications, GLS29EE512 significantly improves better reliability and manufacturability compared with performance and reliability, while lowering power alternate approaches. GLS29EE512 writes with a consumption. GLS29EE512 improves flexibility while single power supply. Internal Erase/Program is lowering the cost for program, data, and configuration transparent to the user. GLS29EE512 conforms to storage applications. JEDEC standard pin assignments for byte-wide To meet high density, surface mount requirements, memories. GLS29EE512 is offered in 32-lead PLCC and 32-lead Featuring high performance Page-Write, TSOP packages. See Figures 1 and 2 for pin GLS29EE512 provides a typical Byte-Write time of 39 assignments. sec. The entire memory, i.e., 64 KByte, can be Device Operation written page-by-page in as little as 2.5 seconds, when using interface features such as Toggle Bit or Data The Greenliant Page-Write EEPROM offers in-circuit Polling to indicate the completion of a Write cycle. To electrical write capability. GLS29EE512 does not protect against inadvertent write, GLS29EE512 have require separate Erase and Program operations. The on-chip hardware and Software Data Protection internally timed Write cycle executes both erase and schemes. Designed, manufactured and tested for a program transparently to the user. GLS29EE512 has wide spectrum of applications, GLS29EE512 is industry standard optional Software Data Protection, offered with a guaranteed Page-Write endurance of which Greenliant recommends always to be enabled. 10,000 cycles. Data retention is rated at greater than GLS29EE512 is compatible with industry standard 100 years. EEPROM pinouts and functionality. These specifications are subject to change without notice. 07/26/2018 2018 Greenliant 1 S71060 GLS FS0019 Rev. 01 GLS29EE512 Small-Sector Flash 512 Kbit (64K x8) Page-Write EEPROM Datasheet 11.000 July 2018 Read The Write operation has three functional cycles: the The Read operations of GLS29EE512 is controlled by Software Data Protection load sequence, the page- CE and OE , both have to be low for the system to load cycle, and the internal Write cycle. The Software obtain data from the outputs. CE is used for device Data Protection consists of a specific three-byte load selection. When CE is high, the chip is deselected sequence that allows writing to the selected page and and only standby power is consumed. OE is the will leave GLS29EE512 protected at the end of the output control and is used to gate data from the output Page-Write. The page-load cycle consists of loading 1 pins. The data bus is in high impedance state when to 128 Bytes of data into the page buffer. The internal either CE or OE is high. Refer to the Read Cycle Write cycle consists of the TBLCO time-out and the Timing diagram for further details (Figure 3). write timer operation. During the Write operation, the Write only valid reads are Data Polling and Toggle Bit. The Page-Write to GLS29EE512 should always use The Page-Write operation allows the loading of up to the JEDEC Standard Software Data Protection (SDP) 128 Bytes of data into the page buffer of three-byte command sequence. GLS29EE512 GLS29EE512 before the initiation of the internal Write contains the optional JEDEC approved Software Data cycle. During the internal Write cycle, all the data in Protection scheme. Greenliant recommends that SDP the page buffer is written simultaneously into the always be enabled, thus, the description of the Write memory array. Hence, the Page-Write feature of operations will be given using the SDP enabled GLS29EE512 allows the entire memory to be written format. The three-byte SDP Enable and SDP Write in as little as 2.5 seconds. During the internal Write commands are identical therefore, any time a SDP cycle, the host is free to perform additional tasks, such Write command is issued, Software Data as to fetch data from other locations in the system to Protection is automatically assured. The first time set up the write to the next page. In each Page-Write the three-byte SDP command is given, the device operation, all the bytes that are loaded into the page becomes SDP enabled. Subsequent issuance of the buffer must have the same page address, i.e. A7 same command bypasses the data protection for the through A16. Any byte not loaded with user data will page being written. At the end of the desired Page- be written to FFH. Write, the entire device remains protected. For See Figures 4 and 5 for the Page-Write cycle timing additional descriptions, please see the application diagrams. If after the completion of the three-byte note, Protecting Against Unintentional Writes When SDP load sequence or the initial byte-load cycle, the Using Single Power Supply Flash Memories. host loads a second byte into the page buffer within a The Write operation consists of three steps. Step 1 is byte-load cycle time (TBLC) of 100 s, GLS29EE512 the three-byte load sequence for Software Data will stay in the page-load cycle. Additional bytes are Protection. Step 2 is the byte-load cycle to a page then loaded consecutively. The page-load cycle will buffer of GLS29EE512. Steps 1 and 2 use the same be terminated if no additional byte is loaded into the timing for both operations. Step 3 is an internally page buffer within 200 s (TBLCO) from the last byte- controlled Write cycle for writing the data loaded in the load cycle, i.e., no subsequent WE or CE high-to- page buffer into the memory array for nonvolatile low transition after the last rising edge of WE or CE . storage. Data in the page buffer can be changed by a subsequent byte-load cycle. The page-load period can During both the SDP three-byte load sequence and continue indefinitely, as long as the host continues to the byte-load cycle, the addresses are latched by the load the device within the byte-load cycle time of 100 falling edge of either CE or WE , whichever occurs s. The page to be loaded is determined by the page last. The data is latched by the rising edge of either address of the last byte loaded. CE or WE , whichever occurs first. The internal Write cycle is initiated by the TBLCO timer after the Software Chip-Erase rising edge of WE or CE , whichever occurs first. GLS29EE512 provides a Chip-Erase operation, which The Write cycle, once initiated, will continue to allows the user to simultaneously clear the entire completion, typically within 5 ms. See Figures 4 and 5 memory array to the 1 state. This is useful when the for WE and CE controlled Page-Write cycle timing entire device must be quickly erased. diagrams and Figures 15 and 17 for flowcharts. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed These specifications are subject to change without notice. 07/26/2018 2018 Greenliant 2 S71060 GLS FS0019 Rev. 01