GLS85LD1001T / GLS85LD512 Industrial Grade PATA NANDrive Fact Sheet 01.000 October 2012 Features Industry Standard ATA / IDE Bus Interface Expanded Data Protection - Host Interface: 16-bit access - WP /PD pin configurable by firmware for 1) - Supports up to PIO Mode-6 prevention of data overwrites 2) Integrated Voltage Detector - Supports up to Multi-Word DMA Mode-4 Detects supply voltage fluctuations and - Supports up to Ultra DMA Mode-4 - generates reset during power-up and power- Performance down to prevent inadvertent writes - Sustained sequential data read - 20-Byte Unique ID for Enhanced Security Up to 30 MByte/sec* - Factory Pre-programmed 10-Byte Unique ID - Sustained sequential data write - Up to 10 MByte/sec* - User-Programmable 10-Byte ID * measured using 128 KByte block size Integrated Voltage Detector Power Management - Prevents inadvertent Write operations due to - 3.3V Power Supply unexpected power-down or brownout. - 5.0V or 3.3V Host Interface Through VDDQ Pre-programmed Embedded Firmware pins - Executes industry standard ATA/IDE - Immediate disabling of unused circuitry commands without host intervention - Implements dynamic wear-leveling algorithms - Zero wake-up latency to substantially increase the longevity of flash Power Specification media - Active mode - Embedded Flash File System 85mA typical (GLS85LD0512) Industrial Temperature Range 100mA typical (GLS85LD1001T) - -40C to 85C for industrial operation - Sleep mode Package 160A typical (GLS85LD0512) - 12mm x 24mm x 1.40mm (maximum height), 170A typical (GLS85LD1001T) 91-ball, 1.0mm ball pitch, LBGA (LBTE) Robust Built-in ECC All Devices are RoHS Compliant Product Description The GLS85LD0512 and GLS85LD1001T Industrial Grade The integrated NAND flash controller with built-in PATA NANDrive devices (referred to as PATA advanced NAND management firmware communicates NANDrive in this datasheet) are high-performance, fully with the Host through the standard ATA protocol. It does integrated, embedded flash solid state drives. They not require any additional or proprietary software such as combine an integrated ATA Controller and 512 MByte or 1 the Flash File System (FFS) and Memory Technology GByte of NAND flash memory in a multi-chip package. Driver (MTD). These products are ideal for solid-state mass storage in The PATA NANDrive provides a WP /PD pin to protect embedded and portable applications that require smaller critical information stored in the flash media from form-factor and more reliable data storage. unauthorized overwrites. The PATA NANDrive is pre- ATA-based solid-state mass storage technology is widely programmed with a 10-Byte unique serial ID and has the used in GPS and telematics, in-vehicle infotainment, option of programming an additional 10-Byte serial ID for portable and industrial computers, handheld data even greater system security. collection scanners, point-of-sale terminals, networking The PATA NANDrives advanced NAND management and telecommunications equipment, robotics, audio and technology enhances data security, improves endurance video recorders, monitoring devices and set-top boxes. and accurately predicts the remaining lifespan of the The PATA NANDrive is a single device, solid state drive NAND flash devices. This innovative technology designed for embedded ATA/IDE protocol systems and combines robust NAND controller hardware error supports standard ATA/IDE protocol with up to PIO Mode- correction capabilities with advanced wear-leveling 1) 2) 6 , Multi-Word DMA Mode-4 and Ultra DMA Mode-4 algorithms and bad block management to significantly interface. The PATA NANDrive device provides complete extend the life of the product. IDE hard disk drive functionality and compatibility in a 12 1) PATA NANDrive is capable of supporting PIO Mode-6, but Identify- mm x 24 mm LBGA package for easy, space-saving Drive information report will show PIO Mode-4 2) PATA NANDrive is capable of supporting Multi-Word DMA Mode-4, mounting to a system motherboard. These products but Identify-Drive information report will show MWDMA Mode-2 surpass traditional storage in their small size, security, reliability, ruggedness and low power consumption. These specifications are subject to change without notice. 10/30/2012 2012 Greenliant Systems 1 S71382-F GLS85LD1001T / GLS85LD512 Industrial Grade PATA NANDrive Fact Sheet 01.000 October 2012 1.0 GENERAL DESCRIPTION Each PATA NANDrive contains an integrated PATA NAND flash memory controller and discrete NAND flash die(s) in a LBGA package. Refer to Figure 2-1 for the PATA NANDrive block diagram. 1.1.6 Error Correction Code (ECC) 1.1 Optimized PATA NANDrive High performance is achieved through optimized The heart of the PATA NANDrive is the PATA NAND hardware error detection and correction. flash memory controller, which translates standard PATA signals into flash media data and control 1.1.7 Serial Communication Interface (SCI) signals. The following components contribute to the The Serial Communication Interface (SCI) is designed PATA NANDrives operation. for manufacturing error reporting. During the design process, always provide access to the SCI port in the 1.1.1 Microcontroller Unit (MCU) PCB design to aid in design validation. The MCU transfers the ATA/IDE commands into data and control signals required for flash media operation. 1.1.8 Multi-tasking Interface 1.1.2 Internal Direct Memory Access (DMA) The multi-tasking interface enables fast, sustained write performance by allowing concurrent Read, The PATA NANDrive uses internal DMA allowing Program and Erase operations to multiple flash media instant data transfer from/to buffer to/from flash media. devices. This implementation eliminates microcontroller overhead associated with the traditional, firmware- 1.2 Advanced NAND Management based approach, thereby increasing the data transfer rate. Advanced NAND management technology balances the wear on erased blocks with an advanced wear- 1.1.3 Power Management Unit (PMU) leveling scheme. Advanced NAND management The PMU controls the power consumption of the technology tracks the number of program/erase cycles PATA NANDrive. The PMU dramatically reduces the within a group. When the Host updates data, higher power consumption of the PATA NANDrive by putting priority is given to the less frequently written erase the part of the circuitry that is not in operation into blocks thereby, evenly distributing host writes within a sleep mode. wear-leveling group. 1.1.4 SRAM Buffer Advanced NAND management technology enhances A key contributor to the PATA NANDrive performance the PATA NANDrive security with password protection is an SRAM buffer. The buffer optimizes the Hosts and four independent protection zones, which can be data transfer to and from the flash media. set to Read-only or Hidden. 1.1.5 Embedded Flash File System The embedded flash file system is an integral part of the PATA NANDrive. It contains MCU firmware that performs the following tasks: 1. Translates host side signals into flash media writes and reads 2. Provides flash media wear leveling to spread the flash writes to increase the longevity of flash media 3. Keeps track of data file structures These specifications are subject to change without notice. 10/30/2012 2012 Greenliant Systems 2 S71382-F