Includes
FLEX 10KA
FLEX 10K
Embedded Programmable
Logic Device Family
January 2003, ver. 4.2 Data Sheet
The industrys first embedded programmable logic device (PLD)
Features...
family, providing System-on-a-Programmable-Chip (SOPC)
integration
Embedded array for implementing megafunctions, such as
efficient memory and specialized logic functions
Logic array for general logic functions
High density
10,000 to 250,000 typical gates (see Tables 1 and 2)
Up to 40,960 RAM bits; 2,048 bits per embedded array block
(EAB), all of which can be used without reducing logic capacity
System-level features
TM
MultiVolt I/O interface support
5.0-V tolerant input pins in FLEX 10KA devices
Low power consumption (typical specification less than 0.5 mA
in standby mode for most devices)
FLEX 10K and FLEX 10KA devices support peripheral
component interconnect Special Interest Group (PCI SIG) PCI
Local Bus Specification, Revision 2.2
FLEX 10KA devices include pull-up clamping diode, selectable
on a pin-by-pin basis for 3.3-V PCI compliance
Select FLEX 10KA devices support 5.0-V PCI buses with eight or
fewer loads
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming any device logic
Table 1. FLEX 10K Device Features
Feature EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50
EPF10K10A EPF10K30A EPF10K50V
Typical gates (logic and RAM) (1) 10,000 20,000 30,000 40,000 50,000
Maximum system gates 31,000 63,000 69,000 93,000 116,000
Logic elements (LEs) 576 1,152 1,728 2,304 2,880
Logic array blocks (LABs) 72 144 216 288 360
Embedded array blocks (EABs) 3 6 6 8 10
Total RAM bits 6,144 12,288 12,288 16,384 20,480
Maximum user I/O pins 150 189 246 189 310
Altera Corporation 1
DS-F10K-4.2FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 2. FLEX 10K Device Features
Feature EPF10K70 EPF10K100 EPF10K130V EPF10K250A
EPF10K100A
Typical gates (logic and 70,000 100,000 130,000 250,000
RAM) (1)
Maximum system gates 118,000 158,000 211,000 310,000
LEs 3,744 4,992 6,656 12,160
LABs 468 624 832 1,520
EABs 9 12 16 20
Total RAM bits 18,432 24,576 32,768 40,960
Maximum user I/O pins 358 406 470 470
Note to tables:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
Devices are fabricated on advanced processes and operate with
...and More
a 3.3-V or 5.0-V supply voltage (see Table 3
Features
In-circuit reconfigurability (ICR) via external configuration
device, intelligent controller, or JTAG port
TM TM
ClockLock and ClockBoost options for reduced clock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices
5.0-V Devices 3.3-V Devices
EPF10K10 EPF10K10A
EPF10K20 EPF10K30A
EPF10K30 EPF10K50V
EPF10K40 EPF10K100A
EPF10K50 EPF10K130V
EPF10K70 EPF10K250A
EPF10K100
2 Altera Corporation