IP-ETH-ETILEHIP Intel

E-tile Hard IP User Guide E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs Updated for Intel Quartus Prime Design Suite: 21.2 Online Version ID: 683468 Send Feedback Version: 2021.08.04 UG-20160Contents Contents 1. About E-tile Hard IP User Guide......................................................................................5 2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core............................................... 6 2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Supported Features.......................................8 2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview................................................... 11 2.3. IP Core Device Family and Speed Grade Support......................................................17 2.3.1. E-Tile Hard IP for Ethernet Intel FPGA IP Device Family Support..................... 17 2.3.2. E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support............ 17 2.4. IP Core Verification.............................................................................................. 18 2.4.1. Simulation Environment............................................................................18 2.4.2. Compilation Checking............................................................................... 18 2.4.3. Hardware Testing.....................................................................................18 2.5. Resource Utilization..............................................................................................18 2.6. Release Information............................................................................................. 20 2.7. Getting Started....................................................................................................21 2.7.1. Installing and Licensing Intel FPGA IP Cores................................................ 21 2.7.2. Specifying the IP Core Parameters and Options............................................24 2.7.3. Generated File Structure...........................................................................25 2.7.4. Integrating Your IP Core in Your Design...................................................... 27 2.7.5. IP Core Testbenches.................................................................................52 2.7.6. Compiling the Full Design..........................................................................53 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters................................................ 53 2.8.1. Parameter Editor Parameters..................................................................... 53 2.8.2. RTL Parameters....................................................................................... 66 2.9. Functional Description.......................................................................................... 68 2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC ............................................. 70 2.9.2. 1588 Precision Time Protocol Interfaces...................................................... 82 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes..................................................105 2.9.4. Auto-Negotiation and Link Training........................................................... 109 2.9.5. TX and RX RS-FEC..................................................................................109 2.9.6. PMA Direct Mode....................................................................................110 2.9.7. Dynamic Reconfiguration.........................................................................110 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example...............................................................110 2.9.9. Ethernet Adaptation Flow with PTP or with External AIB Clocking.................. 112 2.9.10. Ethernet Adaptation Flow with Non-external AIB Clocking.......................... 113 2.10. Reset..............................................................................................................115 2.10.1. Reset Sequence................................................................................... 118 2.11. Interfaces and Signals.......................................................................................120 2.11.1. TX MAC Interface to User Logic.............................................................. 121 2.11.2. RX MAC Interface to User Logic.............................................................. 126 2.11.3. TX PCS Interface to User Logic............................................................... 129 2.11.4. RX PCS Interface to User Logic...............................................................132 2.11.5. FlexE and OTN Mode TX Interface...........................................................135 2.11.6. FlexE and OTN Mode RX Interface...........................................................137 2.11.7. TX Custom PCS Interface to User Logic....................................................139 2.11.8. RX Custom PCS Interface to User Logic................................................... 142 E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Send Feedback Intel FPGA IPs 2