IPR-25GEUMACPHYF Intel

25G Ethernet Intel Stratix 10 FPGA IP User Guide Updated for Intel Quartus Prime Design Suite: 21.1 IP Version: 19.4.0 Online Version ID: 683154 Send Feedback Version: 2021.03.29 UG-20109Contents Contents 1. About the 25G Ethernet Intel FPGA IP............................................................................ 4 1.1. Release Information...............................................................................................8 1.2. 25G Ethernet Intel FPGA IP Supported Features.........................................................9 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support...................10 1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support................................10 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support.......................11 1.4. IP Core Verification.............................................................................................. 11 1.4.1. Simulation Environment............................................................................12 1.4.2. Compilation Checking............................................................................... 12 1.4.3. Hardware Testing.....................................................................................12 1.5. Performance and Resource Utilization..................................................................... 12 2. Getting Started............................................................................................................. 15 2.1. Installing and Licensing Intel FPGA IP Cores............................................................ 15 2.1.1. Intel FPGA IP Evaluation Mode...................................................................16 2.2. Specifying the Intel Stratix 10 IP Core Parameters and Options..................................18 2.3. Simulating the IP Core..........................................................................................18 2.4. Generated File Structure.......................................................................................20 2.5. Integrating Your IP Core in Your Design.................................................................. 22 2.5.1. Pin Assignments...................................................................................... 22 2.5.2. Adding the Transceiver PLL .......................................................................22 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature...................................................................................................25 2.5.4. Placement Settings for the 25G Ethernet Intel FPGA IP Core.......................... 27 2.6. Compiling the Full Design and Programming the FPGA.............................................. 27 3. 25G Ethernet Intel FPGA IP Parameters........................................................................28 4. Functional Description.................................................................................................. 31 4.1. 25G Ethernet Intel FPGA IP Core Functional Description............................................ 31 4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath.......................................32 4.1.2. 25 GbE TX PCS........................................................................................34 4.1.3. TX RS-FEC.............................................................................................. 34 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath...................................... 34 4.1.5. Link Fault Signaling Interface.....................................................................39 4.1.6. 25 GbE RX PCS........................................................................................40 4.1.7. RX RS-FEC..............................................................................................41 4.1.8. Flow Control............................................................................................41 4.1.9. 1588 Precision Time Protocol Interfaces...................................................... 44 4.2. User Interface to Ethernet Transmission..................................................................53 4.2.1. Order of Transmission...............................................................................53 4.2.2. Bit Order For TX and RX Datapaths.............................................................54 5. Reset............................................................................................................................ 55 6. Interfaces and Signal Descriptions............................................................................... 56 6.1. TX MAC Interface to User Logic..............................................................................57 6.2. RX MAC Interface to User Logic..............................................................................59 6.3. Transceivers........................................................................................................61 25G Ethernet Intel Stratix 10 FPGA IP User Guide Send Feedback 2