IPR-ILKN/400G Intel

Interlaken (2nd Generation) Intel FPGA IP User Guide Updated for Intel Quartus Prime Design Suite: 20.2 IP Version: 19.3.0 Subscribe UG-20035 2020.06.22 Send Feedback Latest document on the web: PDF HTMLContents Contents 1. Introduction................................................................................................................... 4 1.1. Features...............................................................................................................5 1.2. Device Family Support............................................................................................8 1.3. Performance and Resource Utilization.......................................................................8 1.4. Flexible Lanes Support..........................................................................................11 1.5. Round-trip Latency...............................................................................................12 1.6. Release Information............................................................................................. 12 2. Getting Started............................................................................................................. 14 2.1. Installing and Licensing Intel FPGA IP Cores............................................................ 14 2.1.1. Intel FPGA IP Evaluation Mode...................................................................15 2.2. Generated File Structure.......................................................................................17 2.3. Specifying the IP Core Parameters and Options........................................................19 2.4. Simulating the IP Core..........................................................................................20 2.5. Compiling the Full Design and Programming the FPGA.............................................. 21 2.6. Integrating Your IP Core in Your Design.................................................................. 21 2.6.1. Pin Assignment........................................................................................21 2.6.2. Adding the External PLL............................................................................21 2.6.3. PMA Adaptation Flow................................................................................22 3. Parameter Settings....................................................................................................... 24 3.1. Main Parameters..................................................................................................24 3.2. PMA Adaptation Parameters...................................................................................27 4. Functional Description.................................................................................................. 31 4.1. Interfaces...........................................................................................................31 4.2. IP Clocks............................................................................................................ 33 4.3. High Level Data Path Flow for Interlaken Mode.........................................................34 4.3.1. Interlaken TX Path................................................................................... 35 4.3.2. Interlaken RX Path...................................................................................39 4.3.3. Unused Transceiver Channels.....................................................................44 4.4. High Level Data Path Flow for Interlaken Look-aside Mode.........................................44 4.4.1. Interlaken Look-aside TX Path................................................................... 46 4.4.2. Interlaken Look-aside RX Path................................................................... 48 4.5. Modes of Operation..............................................................................................50 4.5.1. Interleaved and Packet Modes................................................................... 50 4.5.2. Interlaken Mode...................................................................................... 51 4.5.3. Interlaken Look-aside Mode.......................................................................56 4.5.4. Multi-Segment Mode................................................................................ 59 4.6. Performance........................................................................................................63 4.7. IP Core Reset...................................................................................................... 65 4.8. M20K ECC Support...............................................................................................66 4.9. Out-of-Band Flow Control......................................................................................66 5. Interface Signals.......................................................................................................... 70 5.1. Clock and Reset Interface Signals.......................................................................... 71 5.2. Transmit User Interface Signals............................................................................. 74 5.3. Receive User Interface Signals...............................................................................79 Interlaken (2nd Generation) Intel FPGA IP User Guide Send Feedback 2