Security Supervisor IP (SSIP) for Secure and High Assurance Systems Why Use Alteras SSIP Altera FPGA and SoC products have provided a SSIP is a Logic Locked IP Region long history of user accessible and configurable If you are developing a high security security features for increasingly complex and or anti-tamper application, Alteras sensitive logic designs. These designs include early SSIP design block provides all of the bitstream encryption capabilities in Stratix II, configuration settings. In addition, to more sophisticated static and active features it provides logic to zeroize the device available on modern devices. and its configuration registers upon detection of a tamper event. FPGA designers have historically been responsible for learning about, testing, configuring, and Multiple security certification authorities implementing these security features and capabilities. are already familiar with Alteras SSIP block and can provide simple direction Alteras SSIP block, however, provides a single on how to use the block to ensure system licensable and downloadable logic region dedicated security. This is a key advantage over to accurately and correctly setting the security developing an SSIP of your own. configurations, and providing responses to potential detected attacks. Additional Features of Altera FPGAs e SSTh IP was originally developed as part of a Suitable for Military Applications: complete high security FPGA solution with the SEU Detection and Mitigation Cyclone IIILS low power family of devices. Today, Automatically and continually monitors however, Alteras entire product portfolio brings FPGA configuration R AM for SEU or other er rors these same high assurance and high security features Extended Life Cycles: Altera histor ically to all of your designs, utilizing the SSIP, and provides the longest life c ycles of all following secure design guidelines provided by major FPGA providers, reducing costly authorized government sponsors, will enable faster EOL r isks to program time to develop, test, and certify system security Leaded Packages: Altera provides certifications and requirements for DoD systems. leaded pack age options across near ly all produc t families Reliable Supply Chain: Altera Use Cases and Scenarios Involving SSIP maintains a reputation for robust and reliable supply chains e ATh ltera SSIP block operates continuously as part of an overall high security system. It ensures AQEC Compliance: Altera is par t of that the FPGA is in a known state upon initialization, ensures that the device remains in the the Aerospace Q ualified Elec tronics known state, and enables a design to shut down quickly without compromising sensitive data, Components (AQEC ) wor k ing group in the event that an alarm has been triggered. and previous families hold GEIA- STD -0002-01 cer tifications e SSTh IP is a logic block that has been designed into a specific logic lock region of the FPGA DO-254 Compliance Solutions: so that it interacts directly with the device configuration block (DCB). This gives direct and Combined with cer tified NIOS II sof t low latency access to device monitors and sensors, as well as the partial reconfiguration control embedded processors and third par t y block that is central to the zeroization capability of the SSIP. This logic lock partition is also assessment par tners, Altera has a long essential in making sure that a zeroization process overwrites the entire configuration RAM histor y of use in DO -254 applications space within the device without impacting its own logic structure and terminating a zeroization Advanced Security Features: event before it is complete. Altera has a legac y of secur it y features in all FPGA produc t families to include e SSTh IP block is designed to allow all permutations of FPGA security features to be implemented bitstream encr yption and authentication, in a system. For this reason, it is ideal for use in a product platform where different variants may anti-tamper and anti- cloning features, and now secure boot and code require different security settings (i.e., domestic military sales versus foreign military sales). authentication for Ar r ia 10 S oC ARM Cor tex A9 processorsSSIP Features and Functions Capability Benefits to Secure Communications Systems Monitoring SSIP Provides Control Block Connec tivit y, R edundant monitor ing func tions User S ettings, and D ocumentation to User Watchdog Timer for command/response awareness M onitor Environment Er rors in configuration monitored and repor ted Changes in volatile key value or state Cur rent version (Stratix V ) now includes temperature monitor Status Continuous Status R egister Update SSIP hear tbeat signal generated and monitored Alar ms and tr iggers can be set and controlled by SSIP The cur rent command state and progress of device zeroization Response Key Zeroization and Par tial R econfiguration User alar ms ack nowledged Zeroization of key and entire device configuration R AM through par tial reconfiguration Lock- out of ex ter nal JTAG access (if not already locked out) Can tr i-state all FPGA I/O Supported Devices and Resource Counts (Arria V and Stratix V Available Upon Request) Estimated Registers Memory Support Combinational LUTs 979 466 16K Available as par t of complete cer tified Cyclone IIILS high assurance solution Also compatible with design separation flow and monitor ing of traffic in red and black FPGA regions SSIP licensed, delivered, and cer tified by the United States gover nment Full documentation and licensing ter ms available S olution fielded today in multiple cr yptographic modules and systems 1736 831 14 x M10K Based on Cyclone IIILS SSIP but includes new monitor ing capabilities Zeroization of keys, CR AM, and ER AM now accomplished and ver ified through par tial reconfiguration SSIP suppor ts full range of Cyclone V devices SSIP suppor t of Ar r ia V and Stratix V FPGAs available upon request SSIP Interface to User Logic and Hard Security IP Learn More About SSIP for Altera Devices Learn more about SSIP and other solutions for high assurance and anti-tamper systems by visiting