IP-VITERBI/HS Intel

Viterbi IP Core User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe UG-VITERBI 2017.11.06 Send Feedback Latest document on the web: PDF HTMLContents Contents 1 About the Viterbi IP Core................................................................................................. 3 1.1 Intel DSP IP Core Features.....................................................................................3 1.2 Viterbi IP Core Features...........................................................................................4 1.3 DSP IP Core Device Family Support...........................................................................4 1.4 DSP IP Core Verification...........................................................................................5 1.5 Viterbi IP Core Release Information...........................................................................5 1.6 Viterbi IP Core Performance and Resource Utilization...................................................5 2 Viterbi IP Core Getting Started........................................................................................ 9 2.1 Installing and Licensing Intel FPGA IP Cores...............................................................9 2.1.1 Intel FPGA IP Evaluation Mode......................................................................9 2.1.2 Viterbi IP Core Intel FPGA IP Evaluation Mode Timeout Behavior......................12 2.2 IP Catalog and Parameter Editor............................................................................. 12 2.3 Generating IP Cores (Intel Quartus Prime Pro Edition)................................................14 2.3.1 IP Core Generation Output (Intel Quartus Prime Pro Edition)...........................15 2.4 Simulating Intel FPGA IP Cores...............................................................................18 2.5 DSP Builder for Intel FPGAs Design Flow.................................................................. 18 3 Viterbi IP Core Functional Description........................................................................... 19 3.1 Decoder...............................................................................................................19 3.2 Convolutional Encoder........................................................................................... 19 3.3 Trellis Coded Modulation........................................................................................ 19 3.3.1 Half-Rate Convolutional Codes.................................................................... 20 3.3.2 Trellis Decoder..........................................................................................22 3.3.3 About Converting Received Signals..............................................................23 3.3.4 Trellis Termination.....................................................................................25 3.3.5 Trellis Initialization ................................................................................... 25 3.4 Viterbi IP Core Parameters..................................................................................... 25 3.4.1 Architecture............................................................................................. 25 3.4.2 Code Sets................................................................................................28 3.4.3 Viterbi Parameters.................................................................................... 28 3.4.4 Test Data.................................................................................................30 3.5 Viterbi IP Core Interfaces and Signals......................................................................31 3.5.1 Avalon-ST Interfaces in DSP IP Cores.......................................................... 31 3.5.2 Global Signals.......................................................................................... 32 3.5.3 Avalon-ST Sink Signals.............................................................................. 32 3.5.4 Avalon Source-ST Signals...........................................................................33 3.5.5 Configuration Signals.................................................................................34 3.5.6 Status Signals.......................................................................................... 34 3.5.7 Viterbi IP Core Timing Diagrams................................................................. 35 A Viterbi IP Core User Guide Document Archives.............................................................. 37 5 Document Revision History............................................................................................ 38 Viterbi IP Core User Guide 2