Z-APS-SCH-ESC Intel

Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Last updated for Quartus Prime Design Suite: 16.0 UG-01172 101 Innovation Drive Subscribe 2017.12.28 San Jose, CA 95134 Send Feedback www.altera.comTOC-2 About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Contents About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core... 1-1 Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features....................1-3 Low Latency 40-100GbE IP Core Device Family and Speed Grade Support...................................... 1-4 Device Family Support.................................................................................................................... 1-5 Low Latency 40-100GbE IP Core Device Speed Grade Support............................................... 1-5 IP Core Verification ..................................................................................................................................... 1-6 Simulation Environment.................................................................................................................1-7 Compilation Checking.................................................................................................................... 1-7 Hardware Testing............................................................................................................................. 1-7 Performance and Resource Utilization..................................................................................................... 1-7 Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores..................................... 1-8 Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores...................................... 1-9 Release Information...................................................................................................................................1-10 Getting Started.................................................................................................... 2-1 Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices...................................... 2-2 Licensing IP Cores....................................................................................................................................... 2-3 OpenCore Plus IP Evaluation.........................................................................................................2-3 Specifying the Low Latency 40-100GbE IP Core Parameters and Options......................................... 2-4 IP Core Parameters...................................................................................................................................... 2-5 Files Generated for Stratix V Variations................................................................................................. 2-14 Files Generated for Arria 10 Variations.................................................................................................. 2-15 Integrating Your IP Core in Your Design................................................................................................2-18 Pin Assignments.............................................................................................................................2-19 External Transceiver Reconfiguration Controller Required in Stratix V Designs................ 2-19 Transceiver PLL Required in Arria 10 Designs..........................................................................2-20 External Time-of-Day Module for Variations with 1588 PTP Feature...................................2-22 Clock Requirements for 40GBASE-KR4 Variations..................................................................2-23 External TX MAC PLL..................................................................................................................2-23 Placement Settings for the Low Latency 40-100GbE IP Core..................................................2-23 Low Latency 40-100GbE IP Core Testbenches...................................................................................... 2-23 Low Latency 40-100GbE IP Core Testbench Overview............................................................2-24 Understanding the Testbench Behavior......................................................................................2-27 Simulating the Low Latency 40-100GbE IP Core With the Testbenches........................................... 2-28 Generating the Low Latency 40-100GbE Testbench.................................................................2-29 Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches..........2-30 Simulating with the Modelsim Simulator...................................................................................2-30 Simulating with the NCSim Simulator........................................................................................2-31 Simulating with the VCS Simulator.............................................................................................2-31 Testbench Output Example: Low Latency 40-100GbE IP Core...............................................2-31 Altera Corporation