IS25CD512/010 IS25LD020 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface Output SPI Bus Interface FEATURES Low Power ConMesmumorypt ioWn ith 100 MHz Dual- Single Power Supply Operation - Typical 10 mA active read current Output SPI Bus Interface Memory With 100 MHz Dual- - Low voltage range: 2.70 V 3.60 V (512Kbit / 1Mbit) - Typical 15 mA program/erase current Output SPI Bus Interface 2.30 V 3.60 V (2Mbit) Hardware Write Protection Memory Organization - Protect and unprotect the device from write operation by - IS25CD512: 64K x 8 (512 Kbit) Write Protect (WP ) Pin - IS25CD010: 128K x 8 (1 Mbit) - IS25LD020: 256K x 8 (2 Mbit) Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or Cost Effective Sector/Block Architecture entire memory to be configured as read-only - 512Kb : Uniform 4KByte sectors / Two uniform 32KByte High Product Endurance blocks - 1Mb : Uniform 4KByte sectors / Four uniform 32KByte - Guaranteed 200,000 program/erase cycles per single blocks sector - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte - Minimum 20 years data retention blocks Industrial Standard Pin-out and Package Low standby current 1uA (Typ) - 8-pin SOIC 150mil 512Kb/ 1Mb / 2Mb Serial Peripheral Interface (SPI) Compatible - 8-pin VVSOP 150mil 2Mb - Supports single- or dual-output - 8-pin WSON (5x6 mm) 512 Kb/ 2Mb - Supports SPI Modes 0 and 3 - 8-pin TSSOP 512 Kb / 1Mb / 2Mb - Maximum 33 MHz clock rate for normal read - 8-pin USON (2x3 mm) 512Kb - Maximum 100 MHz clock rate for fast read - KGD (Call Factory) - Lead-free (Pb-free) package Page Program (up to 256 Bytes) Operation - Automotive Temperature Ranges Available - Typical 2 ms per page program Security function Sector, Block or Chip Erase Operation - Built in Safe Guard function and sector unlock function - Maximum 10 ms sector, block or chip erase to make the flash Robust (Appendix1&2) GENERAL DESCRIPTION The IS25CD512/010 and IS25LD020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25CD512/010 and IS25LD020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE ) pins. They comply with all recognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(IS25LD020 is uniform 4 KByte sectors or uniform 64 KByte). The IS25CD512/010 and IS25LD020 are manufactured on pFLASHs advanced non-volatile technology. The devices are offered in a variety of packages for all critical needs. The devices operate at wide temperatures between -40C to +105C. Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D 2/12/2013 IS25CD512/010 IS25LD020 CONNECTION DIAGRAMS CE 1 8 Vcc Vcc CE 8 1 2 7 SO HOLD HOLD SO 7 2 6 SCK 3 WP WP 3 6 SCK 4 5 SIO GND GND 5 SIO 4 8-pin WSON 8-Pin SOIC/VVSOP CE Vcc CE 1 8 Vcc SO 2 7 HOLD HOLD SO WP 3 6 SCK 4 5 GND SIO WP SCK 8-Pin TSSOP GND SIO 8-Pin USON PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE INPUT Chip Enable: CE low activates the devices internal circuitries for device operation. CE high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (SlO), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SIO INPUT/OUTPUT Serial Data Input/Output SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP INPUT Write Protect: A hardware program/erase protection for all or part of a memory array. When the WP pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP is high, the devices are not write-protected. HOLD INPUT Hold: Pause serial communication by the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D 2/12/2013