IS25LD040 4 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface FEATURES Low Power Consumption Single Power Supply Operation - Typical 10 mA active read current - Low voltage range: 2.30 V - 3.60 V - Typical 15 mA program/erase current Memory Organization Hardware Write Protection - IS25LD040: 512K x 8 (4 Mbit) - Protect and unprotect the device from write operation by Write Protect (WP ) Pin Cost Effective Sector/Block Architecture - 4Mb : Uniform 4KByte sectors / Eight uniform Software Write Protection 64KByte blocks - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read- Low standby current 1uA (Typ) only Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output High Product Endurance - Supports SPI Modes 0 and 3 - Guaranteed 200,000 program/erase cycles per - Maximum 33 MHz clock rate for normal read single sector - Maximum 100 MHz clock rate for fast read - Minimum 20 years data retention Page Program (up to 256 Bytes) Operation Industrial Standard Pin-out and Package - Typical 2 ms per page program - 8-pin 150mil SOIC - 8-pin 208mil SOIC Sector, Block or Chip Erase Operation - 8-pin WSON - Maximum 10ms sector, block or chip erase - 8-pin 150mil VVSOP - KGD - Lead-free (Pb-free), package GENERAL DESCRIPTION The IS25LD040 are 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from 2.30 Volt to 3.60 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25LD040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE ) pins. They comply with all recognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks. The IS25LD040 are manufactured on pFLASHs advanced non-volatile technology. The devices are offered in 8-pin 208mil SOIC, 8-pin SOIC 150mil, 8-pin VVSOP 150mil, and 8-pin WSON . The devices operate at wide temperatures between -40C to +105C. Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. D 07/31/2013 IS25LD040 CONNECTION DIAGRAMS CE 1 8 Vcc 8 Vcc CE 1 2 SO 7 HOLD 7 HOLD SO 2 3 6 SCK WP WP 3 6 SCK 4 5 SIO GND GND 5 SIO 4 8-Pin WSON 8-Pin SOIC/VVSOP PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE INPUT Chip Enable: CE low activates the devices internal circuitries for device operation. CE high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SIO INPUT/OUTPUT Serial Data Input/Output SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP INPUT Write Protect: A hardware program/erase protection for all or part of a memory array. When the WP pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP is high, the devices are not write-protected. HOLD INPUT Hold: Pause serial communication by the master device without resetting the serial sequence. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. D 07/31/2013