IS42R86400F/16320F, IS45R86400F/16320F IS42S86400F/16320F, IS45S86400F/16320F 32Mx16, 64Mx8 JULY 2017 512Mb SDRAM DEvIcE O vERvIEW ISSI s 512Mb Synchronous DRAM achieves high-speed FEATURES data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. Clock frequency: 200, 166, 143 MHz The 512Mb SDRAM is organized as follows. Fully synchronous all signals referenced to a positive clock edge PAcKAGE INFORMATION Internal bank for hiding row access/precharge IS42/45S16320F IS42/45S86400F Power supply: Vdd /Vddq = 2.3V-3.6V IS42/45R16320F IS42/45R86400F IS42/45SxxxxxF - Vdd /Vddq = 3.3V 8M x 16 x 4 banks 16M x 8 x 4 banks IS42/45RxxxxxF - Vdd /Vddq = 2.5 54-pin TSOP-II 54-pin TSOP-II LVTTL interface 54-ball TF-BGA Programmable burst length (1, 2, 4, 8, full page) KEY TIMING PARAMETERS Programmable burst sequence: Sequential/Interleave Parameter -5 -6 -7 Unit Auto Refresh (CBR) Clk Cycle Time CAS Latency = 3 5 6 7 ns Self Refresh CAS Latency = 2 10 10 7.5 ns 8K refresh cycles ever y 64 ms Clk Frequency Random column address ever y clock cycle CAS Latency = 3 200 167 143 Mhz CAS Latency = 2 100 100 133 Mhz Programmable CAS latency (2, 3 clocks) Access Time from Clock Burst read/wr ite and burst read/single wr ite CAS Latency = 3 5 5.4 5.4 ns operations capability CAS Latency = 2 6 6 5.4 ns Burst ter mination by burst stop and precharge command ADDRESS TABLE Packages: x8/x16: 54-pin TSOP-II, 54-ball TF-BGA (x16 only) Parameter 32M x 16 64M x 8 Configuration 8M x 16 x 4 16M x 8 x 4 Temperature Range: o o banks banks Commercial (0 C to +70 C) o o Industrial (-40 C to +85 C) Bank Address BA0, BA1 BA0, BA1 o o Automotive, A1 (-40 C to +85 C) Pins/Balls o o Autoprecharge A10/AP A10/AP Automotive, A2 (-40 C to +105 C) Pins/Ball Row Address 8K(A0 A12) 8K(A0 A12) Column 1K(A0 A9) 2K(A0 A9, Address A11) Refresh Count Com./Ind./A1 8K / 64ms 8K / 64ms A2 8K / 16ms 8K / 16ms Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap- plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B1 07/17/2017IS42/45R86400F/16320F IS42/45S86400F/16320F DEvIcE O vERvIEW sequence is available with the AUTO PRECHARGE function The 512Mb SDRAM is a high speed CMOS, dynamic enabled. Precharge one bank while accessing one of the random-access memor y designed to operate in either 3.3V other three banks will hide the precharge cycles and provide Vdd /Vddq or 2.5V Vdd /Vddq memory systems, depending seamless, high-speed, random-access operation. on the DRAM option. Internally configured as a quad-bank DRAM with a synchronous interface. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed The 512Mb SDRAM (536,870,912 bits) includes an AUTO number of locations in a programmed sequence. The REFRESH MODE, and a power-saving, power-down registration of an ACTIVE command begins accesses, mode. All signals are registered on the positive edge of followed by a READ or WRITE command. The ACTIVE the clock signal, CLK. All inputs and outputs are LVTTL command in conjunction with address bits registered are compatible. used to select the bank and row to be accessed (BA0, The 512Mb SDRAM has the ability to synchronously burst BA1 select the bank A0-A12 select the row). The READ data at a high data rate with automatic column-address or WRITE commands in conjunction with address bits generation, the ability to interleave between internal banks registered are used to select the starting column location to hide precharge time and the capability to randomly for the burst access. change column addresses on each clock cycle during Programmable READ or WRITE burst lengths consist of burst access. 1, 2, 4 and 8 locations or full page, with a burst terminate A self-timed row precharge initiated at the end of the burst option. FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN) CLK DQML CKE DQMH COMMAND DATA IN CS DECODER BUFFER RAS 16 16 & CAS CLOCK WE REFRESH MODE 2 GENERATOR DQ 0-15 CONTROLLER REGISTER 13 SELF VDD/VDDQ DATA OUT REFRESH A10 Vss/VssQ BUFFER CONTROLLER 16 16 A12 A11 A9 A8 REFRESH A7 COUNTER A6 A5 8192 A4 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW A0 ROW ADDRESS ADDRESS BA0 LATCH BUFFER BA1 13 13 SENSE AMP I/O GATE 1024 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 10 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 10 2 Integrated Silicon Solution, Inc. www.issi.com Rev. B1 07/17/2017 MULTIPLEXER ROW DECODER