IS49FL004T 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory SEPTEMBER 2013 FEATURES Single Power Supply Operation Firmware HUB (FWH)/Low Pin Count (LPC) - Low voltage range: 3.0 V - 3.6 V Mode - 33 MHz synchronous operation with PCI bus Standard Intel Firmware Hub/LPC Interface - 5-signal communication interface for in-system - Read compatible to Intel 82802 Firmware Hub read and write operations devices - Standard SDP Command Set - Conforms to Intel LPC Interface Specification - Data Polling and Toggle Bit features Revision 1.1 - Register-based read and write protection for each block (FWH mode only) Memory Configuration - 4 ID pins for multiple Flash chips selection - IS49FL004: 512K x 8 (4 Mbit) (FWH mode only) - 5 GPI pins for General Purpose Input Register - TBL pin for hardware write protection to Boot Cost Effective Sector/Block Architecture Block - IS49FL004: One hundred and twenty-eight - WP pin for hardware write protection to whole uniform 4 Kbyte sectors, or eight uniform 64 memory array except Boot Block Kbyte blocks (sector group) Top Boot Block Address/Address Multiplexed (A/A Mux) - IS49FL004: 64 Kbyte top Boot Block Mode - 11-pin multiplexed address and 8-pin data I/O Automatic Erase and Program Operation interface - Build-in automatic program verification for - Supports fast programming on EPROM extended product endurance programmers - Typical 25 s/byte programming time - Standard SDP Command Set - Typical 50 ms sector/block/chip erase time - Data Polling and Toggle Bit features Two Configurable Interfaces - In-System hardware interface: Auto detection of Lower Power Consumption Firmware Hub (FWH) or Low Pin Count (LPC) - Typical 2 mA active read current memory cycle for in-system read and write - Typical 7 mA program/erase current operations - Address/Address-Multiplexed (A/A Mux) High Product Endurance interface for programming on EPROM Pro- - Guarantee 100,000 program/erase cycles per grammers during manufacturing single sector (preliminary) - Minimum 20 years data retention Compatible Pin-out and Packaging - 32-pin (8 mm x 14 mm) VSOP - 32-pin PLCC Hardware Data Protection Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A1 9/19/2013 IS49FL004T GENERAL DESCRIPTION The IS49FL004 is 4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in- system or off-system read, erase and program operations. The 12.0 Volt V power supply are not required for the PP program and erase operations of devices. The devices conform to Intel Low Pin Count (LPC) Interface specification revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications. The IS49FL004 support two configurable interfaces: In-system hardware interface which can automatic de- tect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/ A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory. The memory array of IS49FL004 is divided into uniform 4 Kbyte sectors, or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera- tion. The program operation of IS49FL004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of the devices is executed by issuing the sector, block, or chip erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and erase operations can be detected by reading the Data Polling on I/O7 or Toggle Bit on I/O6. The IS49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled by the TBL pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The rest of blocks except boot block in the devices also can be write protected by WP pin or Block Locking Registers (FWH mode only). The IS49FL004 are manufactured on pFLASHs advanced nonvolatile technology. The devices are offered in 32-pin VSOP and PLCC packages with optional environmental friendly Halogen-free package. Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A1 9/19/2013