IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE NO WAIT STATE BUS SRAM SEPTEMBER 2007 FEATURES DESCRIPTION The 4 Meg NLP/NVP product family feature high-speed, 100 percent bus utilization low-power synchronous static RAMs designed to provide No wait cycles between Read and Wr ite a burstable, high-perfor mance, no wait state, device for Inter nal self-timed wr ite cycle networ king and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 Individual Byte Wr ite Control bits, and 256K words by 18 bits, fabr icated with ISSI s Single R/W (Read/Wr ite) control pin advanced CMOS technology. Clock controlled, registered address, Incor porating a no wait state feature, wait cycles are data and control eliminated when the bus switches from read to write, or wr ite to read. This device integrates a 2-bit burst counter, Inter leaved or linear burst sequence control us- high-speed SRAM core, and high-dr ive capability outputs ing MODE input into a single monolithic circuit. Three chip enables for simple depth expansion All synchronous inputs pass through registers are controlled and address pipelining by a positive-edge-tr iggered single clock input. Operations may be suspended and all synchronous inputs ignored Power Down mode when Clock Enable, CKE is HIGH. In this state the inter nal Common data inputs and data outputs device will hold their previous values. CKE pin to enable clock and suspend operation All Read, Wr ite and Deselect cycles are initiated by the ADV JEDEC 100-pin TQFP, 165-ball PBGA and 119- input. When the ADV is HIGH the inter nal burst counter is incremented. New exter nal addresses can be loaded ball PBGA packages when ADV is LOW. Power supply: Wr ite cycles are inter nally self-timed and are initiated NVP: Vdd 2.5V ( 5%), Vdqd 2.5V ( 5%) by the rising edge of the clock inputs and when WE is NLP: Vdd 3.3V ( 5%), Vqdd 3.3V/2.5V ( 5%) LOW. Separate byte enables allow individual bytes to be Industr ial temperature available written. Lead-free available A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the inter leaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol Parameter -250 -200 Units tkq Clock Access Time 2.6 3.1 ns tck Cycle Time 4 5 ns Frequency 250 200 MHz Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. D 09/10/07IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM 128Kx32 A2-A16 or A2-A17 x 32/x 36: A 0:16 or ADDRESS 128Kx36 x 18: A 0:17 REGISTER 256Kx18 MEMORY ARRAY MODE BURST ADDRESS K DATA-IN A0-A1 A 0-A 1 COUNTER REGISTER K DATA-IN WRITE WRITE CLK CONTROL REGISTER ADDRESS ADDRESS LOGIC K CKE REGISTER REGISTER CE CE2 CE2 CONTROL ADV K REGISTER CONTROL OUTPUT WE LOGIC REGISTER BWX (X=a,b,c,d or a,b) BUFFER OE ZZ 32, 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. www.issi.com Rev. D 09/10/07