CLA40P1200FC V = 2x1200 V RRM High Efficiency Thyristor I = 40 A TAV V = 1.19 V T Phase leg Part number CLA40P1200FC Backside: isolated 2 1 4 5 3 Features / Advantages: Applications: Package: i4-Pac Thyristor for line frequency Line rectifying 50/60 Hz Isolation Voltage: V~ 3000 Planar passivated chip Softstart AC motor control Industry convenient outline Long-term stability DC Motor control RoHS compliant Power converter Epoxy meets UL 94V-0 AC power control Soldering pins for PCB mounting Lighting and temperature control Backside: DCB ceramic Reduced weight Advanced power cycling Disclaimer Notice Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications. Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics. IXYS reserves the right to change limits, conditions and dimensions. Data according to IEC 60747and per semiconductor unless otherwise specified 20191202d 2019 IXYS all rights reservedCLA40P1200FC Ratings Thyristor Symbol Definition Conditions min. typ. max. Unit T = 25C 1300 V V max. non-repetitive reverse/forward blocking voltage RSM/DSM VJ T = 25C 1200 V V max. repetitive reverse/forward blocking voltage RRM/DRM VJ I reverse current, drain current V = 1 2 0 0 V T = 25C 50 A R/D R/D VJ V = 1 2 0 0 V T = 1 2 5 C 4 mA R/D VJ forward voltage drop V I = 4 0 A T = 25C 1.25 V T T VJ I = 8 0 A 1.49 V T T = C 1.19 V I = 4 0 A 125 T VJ I = 8 0 A 1.50 V T average forward current T = 9 5 C T = 1 5 0 C 40 A I TAV C VJ RMS forward current I 180 sine 63 A T(RMS) V T = 1 5 0 C 0.86 V threshold voltage T0 VJ for power loss calculation only slope resistance r 7.9 m T 0.8 K/W R thermal resistance junction to case thJC thermal resistance case to heatsink R 0.2 K/W thCH P total power dissipation T = 25C 150 W tot C max. forward surge current t = 10 ms (50 Hz), sine T = 45C 650 A I TSM VJ t = 8,3 ms (60 Hz), sine V = 0 V 700 A R t = 10 ms (50 Hz), sine T = 1 5 0 C A 555 VJ t = 8,3 ms (60 Hz), sine V = 0 V 595 A R value for fusing It t = 10 ms (50 Hz), sine T = 45C 2.12 kAs VJ t = 8,3 ms (60 Hz), sine V = 0 V 2.04 kAs R t = 10 ms (50 Hz), sine T = 1 5 0 C 1.54 kAs VJ t = 8,3 ms (60 Hz), sine V = 0 V 1.48 kAs R junction capacitance V = 4 0 0 V f = 1 MHz T = 25C 25 pF C J R VJ P max. gate power dissipation t = 30 s T = 1 5 0 C 10 W GM P C t = 300 s 5 W P 0.5 W P average gate power dissipation GAV critical rate of rise of current T = 150C f = 50 Hz repetitive, I = 120 A 150 (di/dt) A/s cr VJ T 0.3 t = 2 0 0 s di /dt = A/s P G I = 0.3A V = V non-repet., I = 40 A 500 A/s G DRM T critical rate of rise of voltage V = V T = 150C 1000 V/s (dv/dt) VJ cr DRM R = method 1 (linear voltage rise) GK gate trigger voltage V V = 6 V T = 25C 1.5 V GT D VJ T = -40C 1.6 V VJ gate trigger current V = 6 V T = 25C 50 mA I VJ GT D T = -40C 80 mA VJ gate non-trigger voltage V V = V T = 150C 0.2 V GD D DRM VJ gate non-trigger current I 3 mA GD latching current t = 10 s T = 25C 125 mA I VJ L p I = 0.3A di /dt = 0.3 A/s G G holding current I V = 6 V R = T = 25C 100 mA H D GK VJ gate controlled delay time t V = V T = 25C 2 s VJ gd D DRM I = 0.3A di /dt = 0.3 A/s G G turn-off time V = 100 V I = 40A V = V T =125 C 200 s t q R T DRM VJ di/dt = 10 A/s dv/dt = 20 V/s t = 200 s p IXYS reserves the right to change limits, conditions and dimensions. Data according to IEC 60747and per semiconductor unless otherwise specified 20191202d 2019 IXYS all rights reserved