IXDP 610 Bus Compatible Digital PWM Controller, IXDP 610 Description The IXDP610 Digital Pulse Width sinking and sourcing 20 mA at TTL Features Modulator (DPWM) is a programmable voltage levels. The Output Disable Microcomputer bus compatible CMOS LSI device which accepts digital logic can be activated either by Two complementary outputs for pulse width data from a microprocessor software or hardware. This facilitates direct control of a switching power and generates two complementary, cycle-by-cycle current-limit, short- bridge non-overlapping, pulse width modula- circuit, over-temperature, and ted signals for direct digital control of desaturation protection schemes. Dynamically programmable pulse switching power bridge. The DPWM is width ranges from 0 to 100 % designed to be operated under the The IXDP610 is capable of operating at Two modes of operation: 7-bit or 8- direct control of a microprocessor and PWM frequencies from zero to 390kHz bit resolution interfaces easily with most standard the dead-time is programmable from Switching frequency range up to microprocessor and microcomputer zero to 14 clock cycles (0 to 11 % of 390 kHz buses. The IXDP610 is packaged in an the PWM cycle), which allows 18-Pin slim DP. operation with fast power MOSFETs, Programmable Dead-time Counter IGBTs, and bipolar power transistors. A prevents switching overlap The PWM waveform generated by the trade-off between PWM frequency and Cycle-by-Cycle disable input to IXDP610 results from comparing the resolution is provided by selecting the protect against over-current, over- output of the Pulse Width counter to counter resolution to be 7-bit or 8-bit. temperature, etc. the number stored in the Pulse Width The 20 mA output drive makes the Latch (see below). A programmable Outputs may be disabled under IXDP610 capable of directly drivingdead-tim is incorporated into the opto isolators and Smart Power software control PWM waveform. The Dead-Time Logic devices. The fast response to pulse Special locking bit prevents damage disables both outputs on each width commands is achieved by to the stage in the event of a transition of the Comparator output for instantaneous change of the outputs to software failure the required dead-time interval. correspond to the new command. This 18-pin slim DIP package eliminates the one-cycle delay usually The output stage provides complemen- associated with other digital PWM tary PWM output signals capable of implementations. Dimensions in inch and mm 18-Pin Slim DIP Symbol Definition Maximum Ratings V Supply voltage -0.3 ... 5.5 V CC V Input voltage -0.3 ... V + 0.3 V IN CC V Output voltage -0.3 ... V + 0.3 V out CC P Maximum power dissipation 500 mW D T Storage temperature range -40 ... 125 C stg 2001 IXYS/DEI All rights reserved 1 OBSOLETEIXDP 610 Symbol Definition Maximum Ratings Numbers in the Fig. 3 to 6 corres- Operating Range ponding to the time values on the min. max. bottom left of this page. V Supply voltage 4.5 5.5 V CC T Operating free air temperature -40 85 C A Symbol Definition/Condition Characteristic Values (Over operating range, unless otherwise specified) min. typ. max. V Input High Voltage ODIS 3.8 V +0.3 V IH(CMOS) CC V Input Low Voltage ODIS -0.3 1.2 V IL(CMOS) V Input Hysteresis ODIS 0.3 0.5 V H V Output High Voltage OUT1 I = -20 mA 2.4 V OH OH OUT2 Fig. 3 Write operation timing diagram V Output Low Voltage OUT1 I = 20 mA 0.4 V OL OL OUT2 V Input High Voltage All Inputs 2.0 V +0.3 V IH(TTL) CC Except ODIS V Input Low Voltage All Inputs -0.3 0.8 V IL(TTL) Except ODIS I Input Leakage All Inputs -10 -0.1 10 A LI Current 0 < V < V I CC I Power Supply f = 5 MHz 3.5 10 mA CC CLK Fig. 4 Output disable to outputs off Current V = V or 0 IH CC timing Symbol Definition/Condition Characteristic Values (T = 25C, V = 5 V 10 %, C1 = 50 pF) A CC OUT 1 or OUT2 No. see -40...85C Fig. 3-6 typ. min. max. WR 1t SEL Stable to WR Low 5 ns AVWL 2t SEL Stable after WR High 10 ns WHAX 3t CS Low to WR Low 5 ns Fig. 5 Stop to outputs off timing SLWL 4t CS High after WR High 5 ns WHSH 5t WR Pulse Width 8 20 ns WLWH 6t Data Valid to WR High 5 ns DVWH OUT1 7t Data Held after WR High 10 20 ns WHDX OUT2 * * WR 8f Clock Frequency 50 050 MHz CLK 9t Clock Pulse Duration Low 12.5 12.5 ns 1 23 CLCH t High 12.5 12.5 ns CHCL CLK 10 t CLK to Output when 5+T ** 5 5+T ns CHOV CLK CLK <5ns 8 9 9 Writing to PW latch 10 11 t ODIS Low to Output Low 20 50 ns ODLOL 12 t WR High to Output Low 30 60 ns Fig. 6 CLOCK to output when writing WHOL When Writing Stop to the to PW latch Control latch 13 t RST Low Time 50 ns RLRH * Output will change 1 rising CLOCK edge +5ns after WR (see Fig. 6) ** T = 1/f clk clk 2001 IXYS/DEI All rights reserved 2 OBSOLETE