Single-Wire Aggregation QuickARTST Evaluation Board This document provides a brief introduction to the Single-Wire Evaluation Kit. J1 RJ45 OW LED0-2-LED Connector (SWA Status) P3B - Program iCE40 or Flash U5 - FTDI (USB to SPI) P12 - Power Supply P-4 Header and Programming (SWA Link and GND) IC1B - SPI Flash U3B iCE40UP5K for SWA FPGA (SWA FPGA) U4 - Audio DAC P3A - Program 2 (I S to Analog) iCE40 or Flash IC1A - SPI Flash J2 - Analog for Overhead FPGA Audio HP Out U3A iCE40UP5K (Overhead FPGA) 2 MK1 - I S Microphone LED 0-8 LED Indicators 2 MK1 - I S Microphone Check Kit Contents The Single-Wire Aggregation (SWA) Evaluation Kit contains the following items: 1 Two Micro-USB Cables Two SWA Evaluation Boards Two Jumper Wires Quick Start Guide Using the SWA Evaluation Kit The Board contains two iCE40UP5K FPGA devices: 2 SWA FPGA - for the actual Single-Wire Aggregation 2 2 Overhead FPGA - for I C, I S and GPIO signal generation and verification. Installing the Software The SWA Evaluation Board is pre-programmed with the Single-Wire Aggregation Demo. 3 Other ready-to-use SWA configurations are available for demonstration and evaluation at www.latticesemi.com/singlewire. Powering the Board and Observing the Demo Program Connect the micro-USB cable to the board. Connect the single-wire link and common ground on 4 the two SWA Evaluation Board through J4 using the two jumper wires. Upon boot up, the SWA demonstration is loaded from SPI Flash to the iCE40UP and starts running. This aggregates the 2 2 I C, I S and GPIO signals. To run the SWA demo: 1. Press and hold the RST SW buttons of both Master and Slave SWA board. 2. Release the button of each SWA board. This resets the SWA FPGA. 3. Simultaneously press the SWS3 buttons of each board. This resets the Overhead FPGA. Single-Wire Aggregation Evaluation Board Note the following after resetting Overhead FPGA. GPIO Signal Aggregation - Overhead FPGAs on Master and Slave SWA Board start sending 6-bit counter GPIO signals to the SWA FPGA for aggregation. It is then de-aggregated by the receiving SWA FPGA. The de-aggregated signals are sent to the receiving Overhead FPGA and LED for verification. - LED 8:3 blinks like a 6-bit counter on both SWA boards. - LED2 blinks on both SWA boards, indicating that the SWA board is receiving 6-bit counter GPIO signals. - Pressing SW1 resets GPIO generation and verification. Pressing SW1 on the transmitting SWA board causes LED2 of the receiving board to turn off because it interrupts the expected 6-bit counter GPIO signals. Pressing SW1 on the receiving SWA board resets the GPIO verification. After this, the LED2 blinks again. 2 I C Signal Aggregation 2 - At Master SWA Board, Press SW0. The Master Overhead FPGA generates nine I C commands to set-up, enable DAC on the Slave SWA Board. 2 - 1 kHz single tone or audio coming from the I S microphone of the Master SWA board is observed on the audio receiver connected on the Slave SWA boards audio jack. 2 - Pressing SW0 again generates I C command to mute and unmute the DAC. 2 I S Signal Aggregation 2 2 2 2 - Master SWA FPGA acts as the I S controllers generating the I S clock and I S WS for the I S 2 microphone and Master Overhead FPGA. I S sampling rate is at ~48 kHz. 2 2 - Master Overhead FPGA generate I S data. I S data sent to Master SWA FPGA are either 2 2 a 1 kHz single tone or I S data coming from I S microphone. Pressing or switching SW2 at 2 Master SWA board selects the I S data sent to Master SWA FPGA. 2 - De-aggregated I S data from Slave SWA board are sent to Slave Overhead FPGA to verify if it is receiving a 1 kHz single tone. Same signals are sent to DAC so that you can verify the 2 received audio through audio jack. LED0 on Slave SWA FPGA indicates the status of I S data verification. Blinking LED0 means it is receiving expected single tone data. 2 - Switching SW2 at Slave SWA board resets I S verification being done by Slave Overhead FPGA. 2 - I S Signals also feedback to Master Overhead FPGA. After resetting Master Overhead FPGA, Master SWA LED0 blinks, which indicates that it is sending 1 kHz single tone signal to SWA FPGA. 2 - Switching Slave SWA Board SW2 resets I S verification. Doing More with the Single Wire Evaluation Kit Check the Lattice website at www.latticesemi.com/single-wire to download the full Users Guide, 5 PC-based software tools to interact with the demonstration program, and other resources. Additional Terms and Conditions Applicable to Lattice Programming and Development Hardware Lattice device programmers, programming cables, socket adapters, and other hardware sold for use in conjunction with Lattice software (Programming Hardware) and Lattice evaluation boards and development kits sold for use in conjunction with evaluating Lattice products (Development Hardware) are designed and intended for use solely with semiconductor components manufactured by Lattice Semiconductor Corporation. Programming and Development Hardware is warranted to meet Lattice specifications only for a period of ninety (90) days in all other respects the terms and conditions of sale of Programming and Development Hardware shall be Lattices standard terms and conditions set forth in Lattices Sales Order Acknowledgment. Additionally, Lattice specifications for Programming and Development Hardware limit their use to low-volume engineering applications only, and not for volume production use. The warranty for Programming and Development Hardware will not apply to any Programming or Development Hardware used in production, used with worn or improperly installed hardware, or used with incompatible systems or components. Technical Support www.latticesemi.com/support Copyright 2020 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., Lattice (design) are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. QS052 V1 August 2020