ispLSI 1016/883 In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC High-Speed Global Interconnect 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs 96 Registers Wide Input Gating for Fast Counters, State A0 B7 Machines, Address Decoders, etc. DQ B6 A1 Small Logic Block Size for Random Logic DQ B5 Security Cell Prevents Unauthorized Copying A2 Logic 2 HIGH PERFORMANCE E CMOS TECHNOLOGY GLB B4 A3 Array DQ fmax = 60 MHz Maximum Operating Frequency A4 B3 tpd = 20 ns Propagation Delay DQ TTL Compatible Inputs and Outputs A5 B2 Electrically Erasable and Reprogrammable B1 A6 2 Non-Volatile E CMOS Technology Global Routing Pool (GRP) 100% Tested A7 B0 IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP) 5-Volt Only CLK Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging COMBINES EASE OF USE AND THE FAST SYSTEM Description SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS The ispLSI 1016/883 is a High-Density Programmable Complete Programmable Device Can Combine Glue Logic Device processed in full compliance to MIL-STD- Logic and Structured Designs 883. This military grade device contains 96 Registers, 32 Three Dedicated Clock Input Pins Universal I/O pins, four Dedicated Input pins, three Dedi- Synchronous and Asynchronous Clocks Flexible Pin Placement cated Clock Input pins and a Global Routing Pool (GRP). Optimized Global Routing Pool Provides Global The GRP provides complete interconnectivity between Interconnectivity all of these elements. The ispLSI 1016/883 features 5- Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the intercon- nect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1016/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 1016/883 Functional Block Diagram Figure 1. ispLSI 1016/883 Functional Block Diagram Generic Logic Blocks (GLBs) IN 3 MODE/IN 2 I/O 31 B7 I/O 30 I/O 0 I/O 29 A0 I/O 1 B6 I/O 28 I/O 2 I/O 3 A1 I/O 27 B5 I/O 26 I/O 4 I/O 25 A2 I/O 5 B4 I/O 24 Global I/O 6 Routing A3 I/O 7 I/O 23 Pool B3 I/O 22 (GRP) I/O 8 A4 I/O 21 I/O 9 B2 I/O 20 I/O 10 A5 I/O 11 I/O 19 B1 I/O 18 I/O 12 A6 I/O 17 B 0 I/O 13 I/O 16 I/O 14 A7 I/O 15 SDI/IN 0 CLK 0 SDO/IN 1 CLK 1 Clock CLK 2 Distribution IOCLK 0 Network IOCLK 1 Megablock ispEN Y0 *Note: Y1 and RESET Y1/RESET* are multiplexed SCLK/Y2 on the same pin 0139B(1a)-isp.eps The device also has 32 I/O cells, each of which is directly The GRP has as its inputs the outputs from all of the GLBs connected to an I/O pin. Each I/O cell can be individually and all of the inputs from the bi-directional I/O cells. All of programmed to be a combinatorial input, registered in- these signals are made available to the inputs of the put, latched input, output or bi-directional I/O pin with GLBs. Delays through the GRP have been equalized to 3-state control. Additionally, all outputs are polarity minimize timing skew. selectable, active high or active low. The signal levels are Clocks in the ispLSI 1016/883 device are selected using TTL compatible voltages and the output drivers can the Clock Distribution Network. Three dedicated clock source 4 mA or sink 8 mA. pins (Y0, Y1 and Y2) are brought into the distribution Eight GLBs, 16 I/O cells, two dedicated inputs and one network, and five clock outputs (CLK 0, CLK 1, CLK 2, ORP are connected together to make a Megablock (see IOCLK 0 and IOCLK 1) are provided to route clocks to the figure 1). The outputs of the eight GLBs are connected to GLBs and I/O cells. The Clock Distribution Network can a set of 16 universal I/O cells by the ORP. The ispLSI also be driven from a special clock GLB (B0 on the ispLSI 1016/883 device contains two of these Megablocks. 1016/883 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. 2 DEVICE HAS BEEN DISCONTINUED PER PCN 05A-10 Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) lnput Bus