ispLSI 1032 Device Datasheet September 2010 All Devices Discontinued Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 1032-60LT ispLSI 1032-80LT ispLSI 1032-90LT ispLSI 1032-60LTI PCN 13-10 ispLSI 1032-60LJ ispLSI 1032 Discontinued ispLSI 1032-80LJ ispLSI 1032-90LJ ispLSI 1032-60LJI ispLSI 1016-60LH/883 PCN 05A-10 5962-9476201MXC 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: ispLSI 1032 In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC High Speed Global Interconnect Output Routing Pool 6000 PLD Gates 64 I/O Pins, Eight Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0 192 Registers Wide Input Gating for Fast Counters, State A0 C7 Machines, Address Decoders, etc. DQ A1 C6 Small Logic Block Size for Fast Random Logic Security Cell Prevents Unauthorized Copying C5 A2 DQ Logic 2 HIGH PERFORMANCE E CMOS TECHNOLOGY GLB A3 C4 Array DQ fmax = 90 MHz Maximum Operating Frequency A4 C3 fmax = 60 MHz for Industrial and Military/883 Devices DQ tpd = 12 ns Propagation Delay A5 C2 TTL Compatible Inputs and Outputs A6 C1 Electrically Erasable and Reprogrammable 2 Non-Volatile E CMOS Technology Global Routing Pool (GRP) A7 C0 100% Tested IN-SYSTEM PROGRAMMABLE B0 B1 B2 B3 B4 B5 B6 B7 CLK In-System Programmable (ISP) 5-Volt Only Output Routing Pool Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping COMBINES EASE OF USE AND THE FAST SYSTEM Description SPEED OF PLDs WITH THE DENSITY AND FLEX- The ispLSI 1032 is a High-Density Programmable Logic IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Device containing 192 Registers, 64 Universal I/O pins, Complete Programmable Device Can Combine Glue Logic and Structured Designs eight Dedicated Input pins, four Dedicated Clock Input Four Dedicated Clock Input Pins pins and a Global Routing Pool (GRP). The GRP pro- Synchronous and Asynchronous Clocks vides complete interconnectivity between all of these Flexible Pin Placement elements. The ispLSI 1032 features 5-Volt in-system Optimized Global Routing Pool Provides Global programming and in-system diagnostic capabilities. It is Interconnectivity the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1032 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI 1032 device. Each GLB has 18 inputs, a program- mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556