ispLSI 1032E In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC 6000 PLD Gates Output Routing Pool 64 I/O Pins, Eight Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0 192 Registers A0 C7 DQ High Speed Global Interconnect A1 C6 Wide Input Gating for Fast Counters, State A2 DQ C5 Logic Machines, Address Decoders, etc. A3 GLB C4 Array DQ Small Logic Block Size for Random Logic A4 C3 2 DQ HIGH PERFORMANCE E CMOS TECHNOLOGY A5 C2 fmax = 125 MHz Maximum Operating Frequency A6 C1 tpd = 7.5 ns Propagation Delay Global Routing Pool (GRP) A7 C0 TTL Compatible Inputs and Outputs B0 B1 B2 B3 B4 B5 B6 B7 CLK Electrically Erasable and Reprogrammable Output Routing Pool Non-Volatile 0139A(A1)-isp 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power Description IN-SYSTEM PROGRAMMABLE The ispLSI 1032E is a High Density Programmable Logic In-System Programmable (ISP) 5V Only Device containing 192 Registers, 64 Universal I/O pins, Increased Manufacturing Yields, Reduced Time-to- eight Dedicated Input pins, four Dedicated Clock Input Market and Improved Product Quality pins and a Global Routing Pool (GRP). The GRP Reprogram Soldered Devices for Faster Prototyping provides complete interconnectivity between all of these OFFERS THE EASE OF USE AND FAST SYSTEM elements. The ispLSI 1032E device offers 5V non-vola- SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY tile in-system programmability of the logic, as well as the OF FIELD PROGRAMMABLE GATE ARRAYS interconnects to provide truly reconfigurable systems. A Complete Programmable Device Can Combine Glue functional superset of the ispLSI 1032 architecture, the Logic and Structured Designs ispLSI 1032E device adds two new global output enable Enhanced Pin Locking Capability pins. Four Dedicated Clock Input Pins The basic unit of logic on the ispLSI 1032E device is the Synchronous and Asynchronous Clocks Generic Logic Block (GLB). The GLBs are labeled A0, A1D7 (see Figure 1). There are a total of 32 GLBs in the Programmable Output Slew Rate Control to Minimize Switching Noise ispLSI 1032E device. Each GLB has 18 inputs, a pro- grammable AND/OR/Exclusive OR array, and four outputs Flexible Pin Placement which can be configured to be either combinatorial or Optimized Global Routing Pool Provides Global registered. Inputs to the GLB come from the GRP and Interconnectivity dedicated inputs. All of the GLB outputs are brought back Lead-Free Package Options into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 1032E Functional Block Diagram Figure 1. ispLSI 1032E Functional Block Diagram RESET Input Bus Generic Output Routing Pool (ORP) Logic Blocks (GLBs) GOE 1/IN 5 D7 D6 D5 D4 D3 D2 D1 D0 GOE 0/IN 4 I/O 47 C7 I/O 46 I/O 0 I/O 45 A0 I/O 1 C6 I/O 44 I/O 2 I/O 3 A1 I/O 43 C5 I/O 42 I/O 4 I/O 41 A2 I/O 5 C4 I/O 40 Global I/O 6 Routing A3 I/O 7 I/O 39 C3 Pool I/O 38 I/O 8 (GRP) A4 I/O 37 I/O 9 C2 I/O 36 I/O 10 A5 I/O 11 C1 I/O 35 I/O 34 I/O 12 A6 I/O 33 C0 I/O 13 I/O 32 I/O 14 A7 I/O 15 SDI/IN 0 CLK 0 B0 B1 B2 B3 B4 B5 B6 B7 MODE/IN 1 CLK 1 Clock CLK 2 Distribution IOCLK 0 Network Output Routing Pool (ORP) IOCLK 1 Megablock Input Bus ispEN The device also has 64 I/O cells, each of which is directly The GRP has, as its inputs, the outputs from all of the connected to an I/O pin. Each I/O cell can be individually GLBs and all of the inputs from the bi-directional I/O cells. programmed to be a combinatorial input, registered in- All of these signals are made available to the inputs of the put, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to I/O pin with 3-state control. The signal levels are TTL minimize timing skew. compatible voltages and the output drivers can source 4 Clocks in the ispLSI 1032E device are selected using the mA or sink 8 mA. Each output can be programmed Clock Distribution Network. Four dedicated clock pins independently for fast or slow output slew rate to mini- (Y0, Y1, Y2 and Y3) are brought into the distribution mize overall output switching noise. network, and five clock outputs (CLK 0, CLK 1, CLK 2, Eight GLBs, 16 I/O cells, two dedicated inputs and one IOCLK 0 and IOCLK 1) are provided to route clocks to the ORP are connected together to make a Megablock (see GLBs and I/O cells. The Clock Distribution Network can Figure 1). The outputs of the eight GLBs are connected also be driven from a special clock GLB (C0 on the ispLSI to a set of 16 universal I/O cells by the ORP. Each ispLSI 1032E device). The logic of this GLB allows the user to 1032E device contains four Megablocks. create an internal clock from a combination of internal signals within the device. 2 USE ispLSI 1032EA FOR NEW DESIGNS lnput Bus Output Routing Pool (ORP) SDO/IN 2 SCLK/IN 3 I/O 16 I/O 17 I/O 63 I/O 18 I/O 62 I/O 19 I/O 61 I/O 60 I/O 20 I/O 21 I/O 59 I/O 22 I/O 58 I/O 23 I/O 57 I/O 56 I/O 24 I/O 25 I/O 55 I/O 26 I/O 54 I/O 27 I/O 53 I/O 52 I/O 28 I/O 29 I/O 51 I/O 30 I/O 50 I/O 31 I/O 49 I/O 48 Y0 IN 7 Y1 IN 6 Y2 Y3 Output Routing Pool (ORP) lnput Bus