ispLSI 1032EA In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC 6000 PLD Gates Output Routing Pool 64 I/O Pins, Four Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0 192 Registers High Speed Global Interconnect A0 C7 DQ Wide Input Gating for Fast Counters, State A1 C6 Machines, Address Decoders, etc. DQ A2 C5 Small Logic Block Size for Random Logic Logic Functionally Compatible with ispLSI 1032E A3 C4 GLB Array DQ NEW FEATURES A4 C3 100% IEEE 1149.1 Boundary Scan Testable DQ A5 C2 ispJTAG In-System Programmable via IEEE 1149.1 A6 C1 (JTAG) Test Access Port Global Routing Pool (GRP) A7 C0 User Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin) B0 B1 B2 B3 B4 B5 B6 B7 CLK Open-Drain Output Option Output Routing Pool 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 200 MHz Maximum Operating Frequency 0139A/1032EA tpd = 4.5 ns Propagation Delay TTL Compatible Inputs and Outputs Description Electrically Erasable and Reprogrammable Non-Volatile The ispLSI 1032EA is a High Density Programmable 100% Tested at Time of Manufacture Logic Device containing 192 Registers, 64 Universal I/O Unused Product Term Shutdown Saves Power pins, four Dedicated Input pins, four Dedicated Clock IN-SYSTEM PROGRAMMABLE Input pins and a Global Routing Pool (GRP). The GRP Increased Manufacturing Yields, Reduced Time-to- provides complete interconnectivity between all of these Market and Improved Product Quality elements. The ispLSI 1032EA features 5V in-system Reprogram Soldered Devices for Faster Prototyping programmability (ISP) and in-system diagnostic capa- OFFERS THE EASE OF USE AND FAST SYSTEM bilities via IEEE 1149.1 Test Access Port. The ispLSI SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY 1032EA device offers non-volatile reprogrammability of OF FIELD PROGRAMMABLE GATE ARRAYS the logic, as well as the interconnects to provide truly Complete Programmable Device Can Combine Glue reconfigurable systems. A functional superset of the Logic and Structured Designs Enhanced Pin Locking Capability ispLSI 1032 architecture, the ispLSI 1032EA device adds Four Dedicated Clock Input Pins user selectable 3.3V or 5V I/O and open-drain output Synchronous and Asynchronous Clocks options. Programmable Output Slew Rate Control to Minimize Switching Noise The basic unit of logic on the ispLSI 1032EA device is the Flexible Pin Placement Generic Logic Block (GLB). The GLBs are labeled A0, Optimized Global Routing Pool Provides Global A1D7 (Figure 1). There are a total of 32 GLBs in the Interconnectivity ispLSI 1032EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinato- rial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 1032EA Functional Block Diagram Figure 1. ispLSI 1032EA Functional Block Diagram RESET Input Bus VCCIO Generic Output Routing Pool (ORP) Logic Blocks (GLBs) GOE 1/IN 5 D7 D6 D5 D4 D3 D2 D1 D0 GOE 0/IN 4 I/O 47 C7 I/O 46 I/O 0 I/O 45 A0 I/O 1 C6 I/O 44 I/O 2 I/O 3 A1 I/O 43 C5 I/O 42 I/O 4 A2 I/O 41 I/O 5 C4 I/O 40 Global I/O 6 A3 Routing I/O 7 I/O 39 C3 Pool I/O 38 I/O 8 A4 (GRP) I/O 37 C2 I/O 9 I/O 36 I/O 10 A5 I/O 11 I/O 35 C1 I/O 34 I/O 12 A6 I/O 33 C0 I/O 13 I/O 32 I/O 14 A7 I/O 15 CLK 0 B0 B1 B2 B3 B4 B5 B6 B7 CLK 1 Clock TDI CLK 2 Megablock Distribution IOCLK 0 Network Output Routing Pool (ORP) IOCLK 1 TDO TMS Input Bus TCK 0139B/1032EA The device also has 64 I/O cells, each of which is directly Clocks in the ispLSI 1032EA device are selected using connected to an I/O pin. Each I/O cell can be individually the Clock Distribution Network. Four dedicated clock pins programmed to be a combinatorial input, registered (Y0, Y1, Y2 and Y3) are brought into the distribution input, latched input, output or bi-directional network, and five clock outputs (CLK 0, CLK 1, CLK 2, I/O pin with 3-state control. The signal levels are TTL IOCLK 0 and IOCLK 1) are provided to route clocks to the compatible voltages and the output drivers can source GLBs and I/O cells. The Clock Distribution Network can 2mA or sink 8mA. Each output can be programmed also be driven from a special clock GLB (C0 on the ispLSI independently for fast or slow output slew rate to 1032EA device). The logic of this GLB allows the user to minimize overall output switching noise. By connecting create an internal clock from a combination of internal the VCCIO pin to a common 5V or 3.3V power supply, signals within the device. I/O output levels can be matched to 5V or 3.3V-compat- Programmable Open-Drain Outputs ible voltages. In addition to the standard output configuration, the Eight GLBs, 16 I/O cells, dedicated inputs (if available) outputs of the ispLSI 1032EA are individually program- and one ORP are connected together to make a mable, either as a standard totem-pole output or an Megablock (Figure 1). The outputs of the eight GLBs are open-drain output. The totem-pole output drives the connected to a set of 16 universal I/O cells by the ORP. specified Voh and Vol levels, whereas the open-drain Each ispLSI 1032EA device contains four Megablocks. output drives only the specified Vol. The Voh level on the The GRP has, as its inputs, the outputs from all of the open-drain output depends on the external loading and GLBs and all of the inputs from the bi-directional I/O cells. pull-up. This output configuration is controlled by a pro- All of these signals are made available to the inputs of the grammable fuse. The default configuration when the GLBs. Delays through the GRP have been equalized to device is in bulk erased state is totem-pole configuration. minimize timing skew. The open-drain/totem-pole option is selectable through the Lattice software tools. 2 USE ispMACH 4A5 FOR NEW 5V DESIGNS lnput Bus Output Routing Pool (ORP) I/O 16 I/O 17 I/O 63 I/O 18 I/O 62 I/O 19 I/O 61 I/O 60 I/O 20 I/O 21 I/O 59 I/O 22 I/O 58 I/O 23 I/O 57 I/O 56 I/O 24 I/O 25 I/O 55 I/O 26 I/O 54 I/O 27 I/O 53 I/O 52 I/O 28 I/O 29 I/O 51 I/O 30 I/O 50 I/O 31 I/O 49 I/O 48 Y0 IN 7 Y1 IN 6 Y2 Y3 Output Routing Pool (ORP) lnput Bus