ispLSI 1048 Device Datasheet September 2010 All Devices Discontinued Product Change Notification (PCN) 13-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 1048-50LQ ispLSI 1048-70LQ ispLSI 1048 Discontinued PCN 13-10 ispLSI 1048-80LQ ispLSI 1048-50LQI 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: ispLSI 1048 In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 8000 PLD Gates Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 96 I/O Pins, Ten Dedicated Inputs 288 Registers A0 D7 DQ High-Speed Global Interconnects A1 D6 A2 D5 Wide Input Gating for Fast Counters, State DQ Logic A3 D4 Machines, Address Decoders, etc. Global Routing Pool (GRP) GLB Array A4 DQ D3 Small Logic Block Size for Random Logic A5 D2 Security Cell Prevents Unauthorized Copying DQ D1 A6 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A7 D0 fmax = 80 MHz Maximum Operating Frequency B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 CLK fmax = 50 MHz for Industrial Devices Output Routing Pool Output Routing Pool tpd = 15 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable 2 Non-Volatile E CMOS Technology Description 100% Tested The ispLSI 1048 is a High-Density Programmable Logic IN-SYSTEM PROGRAMMABLE Device which contain 288 Registers, 96 Universal I/O In-System Programmable (ISP) 5-Volt Only Increased Manufacturing Yields, Reduced Time-to- pins, ten Dedicated Input pins, four Dedicated Clock Market, and Improved Product Quality Input pins and a Global Routing Pool (GRP). The GRP Reprogram Soldered Devices for Faster Debugging provides complete interconnectivity between all of these COMBINES EASE OF USE AND THE FAST SYSTEM elements. The ispLSI 1048 features 5-Volt in-system SPEED OF PLDs WITH THE DENSITY AND FLEX- programming and in-system diagnostic capabilities. It is IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS the first device which offers non-volatile reprogrammability Complete Programmable Device Can Combine Glue of the logic, as well as the interconnect to provide truly Logic and Structured Designs reconfigurable systems. Four Dedicated Clock Input Pins Synchronous and Asynchronous Clocks The basic unit of logic on the ispLSI 1048 devices is the Flexible Pin Placement Generic Logic Block (GLB). The GLBs are labeled A0, A1 Optimized Global Routing Pool Provides Global .. F7 (see figure 1). There are a total of 48 GLBs in the Interconnectivity ispLSI 1048 device. Each GLB has 18 inputs, a program- mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556