ispLSI 1048E In-System Programmable High Density PLD Features Functional Block Diagram HIGH DENSITY PROGRAMMABLE LOGIC Output Routing Pool Output Routing Pool 8,000 PLD Gates F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 96 I/O Pins, Twelve Dedicated Inputs A0 D7 288 Registers DQ A1 D6 A2 D5 High-Speed Global Interconnects DQ Logic A3 D4 Wide Input Gating for Fast Counters, State Global Routing Pool (GRP) GLB Array A4 DQ D3 Machines, Address Decoders, etc. A5 D2 DQ A6 D1 Small Logic Block Size for Random Logic A7 D0 Functionally and Pin-out Compatible to ispLSI 1048C B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 CLK 2 HIGH PERFORMANCE E CMOS TECHNOLOGY Output Routing Pool Output Routing Pool fmax = 125 MHz Maximum Operating Frequency 0139G1A-isp tpd = 7.5 ns Propagation Delay TTL Compatible Inputs and Outputs Description Electrically Eraseable and Reprogrammable The ispLSI 1048E is a High Density Programmable Logic Non-Volatile Device containing 288 Registers, 96 Universal I/O pins, 100% Tested at Time of Manufacture 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing IN-SYSTEM PROGRAMMABLE Pool (GRP). The GRP provides complete interconnectivity In-System Programmable (ISP) 5V Only between all of these elements. The ispLSI 1048E offers Increased Manufacturing Yields, Reduced Time-to- 5V non-volatile in-system programmability of the logic, as Market and Improved Product Quality well as the interconnect to provide truly reconfigurable Reprogram Soldered Devices for Faster Prototyping systems. A functional superset of the ispLSI 1048 archi- OFFERS THE EASE OF USE AND FAST SYSTEM tecture, the ispLSI 1048E device adds two new global SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY output enable pins and two additional dedicated inputs. OF FIELD PROGRAMMABLE GATE ARRAYS The basic unit of logic on the ispLSI 1048E device is the Complete Programmable Device Can Combine Glue Generic Logic Block (GLB). The GLBs are labeled A0, Logic and Structured Designs A1F7 (see Figure 1). There are a total of 48 GLBs in the Enhanced Pin Locking Capability ispLSI 1048E device. Each GLB has 18 inputs, a pro- Four Dedicated Clock Input Pins grammable AND/OR/Exclusive OR array, and four outputs Synchronous and Asynchronous Clocks which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and Programmable Output Slew Rate Control to dedicated inputs. All of the GLB outputs are brought back Minimize Switching Noise into the GRP so that they can be connected to the inputs Flexible Pin Placement of any other GLB on the device. Optimized Global Routing Pool Provides Global Interconnectivity Lead-Free Package Options Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 1048E Functional Block Diagram Figure 1. ispLSI 1048E Functional Block Diagram I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 11 10 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8 RESET Input Bus Input Bus GOE 0 Generic Output Routing Pool (ORP) Output Routing Pool (ORP) GOE 1 Logic Blocks (GLBs) IN 7 F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 IN 6 I/O 63 D7 I/O 62 I/O 61 I/O 0 A0 D6 I/O 1 I/O 60 I/O 2 I/O 59 I/O 3 A1 D5 I/O 58 I/O 57 I/O 4 Global A2 D4 I/O 56 I/O 5 I/O 6 Routing A3 I/O 7 I/O 55 D3 Pool I/O 54 I/O 53 I/O 8 A4 D2 (GRP) I/O 52 I/O 9 I/O 10 A5 I/O 51 I/O 11 D1 I/O 50 I/O 49 I/O 12 A6 D0 I/O 48 I/O 13 I/O 14 A7 I/O 15 SDI/IN 0 CLK 0 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 MODE/IN 1 CLK 1 Clock CLK 2 Distribution IOCLK 0 Network Output Routing Pool (ORP) Output Routing Pool (ORP) IOCLK 1 Megablock Input Bus Input Bus ispEN IN 2 SDO/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN SCLK/ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Y Y Y Y IN 3 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 4 IN 5 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 0 1 2 3 0139F(2)-48B-isp The device also has 96 I/O cells, each of which is directly The GRP has, as its inputs, the outputs from all of the connected to an I/O pin. Each I/O cell can be individually GLBs and all of the inputs from the bi-directional I/O cells. programmed to be a combinatorial input, registered in- All of these signals are made available to the inputs of the put, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to I/O pin with 3-state control. The signal levels are TTL minimize timing skew. compatible voltages and the output drivers can source 4 Clocks in the ispLSI 1048E device are selected using the mA or sink 8 mA. Each output can be programmed Clock Distribution Network. Four dedicated clock pins independently for fast or slow output slew rate to mini- (Y0, Y1, Y2 and Y3) are brought into the distribution mize overall output switching noise. network, and five clock outputs (CLK 0, CLK 1, CLK 2, Eight GLBs, 16 I/O cells, two dedicated inputs and one IOCLK 0 and IOCLK 1) are provided to route clocks to the ORP are connected together to make a Megablock (see GLBs and I/O cells. The Clock Distribution Network can figure 1). The outputs of the eight GLBs are connected to also be driven from a special clock GLB (D0). The logic a set of 16 universal I/O cells by the ORP. Each ispLSI of this GLB allows the user to create an internal clock 1048E device contains six Megablocks. from a combination of internal signals within the device. 2 USE ispLSI 1048EA FOR NEW DESIGNS Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) lnput Bus