Select devices have been discontinued. See Ordering Information section for product status. ispLSI 2032/A In-System Programmable High Density PLD Features Functional Block Diagram ENHANCEMENTS ispLSI 2032A is Fully Form and Function Compatible to the ispLSI 2032, with Identical Timing Specifcations and Packaging ispLSI 2032A is Built on an Advanced 0.35 Micron 2 CMOS Technology E HIGH DENSITY PROGRAMMABLE LOGIC Global Routing Pool A0 A7 (GRP) 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs A1 A6 DQ 32 Registers DQ High Speed Global Interconnect Logic Wide Input Gating for Fast Counters, State A2 GLB Array DQ A5 Machines, Address Decoders, etc. DQ Small Logic Block Size for Random Logic A3 A4 2 HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay TTL Compatible Inputs and Outputs 0139Bisp/2000 Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power Description IN-SYSTEM PROGRAMMABLE The ispLSI 2032 and 2032A are High Density Program- In-System Programmable (ISP) 5V Only mable Logic Devices. The devices contain 32 Registers, Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality 32 Universal I/O pins, two Dedicated Input Pins, three Reprogram Soldered Devices for Faster Prototyping Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY provides complete interconnectivity between all of these OF FIELD PROGRAMMABLE GATE ARRAYS elements. The ispLSI 2032 and 2032A feature 5V in- Complete Programmable Device Can Combine Glue system programmability and in-system diagnostic Logic and Structured Designs capabilities. The ispLSI 2032 and 2032A offer non- Enhanced Pin Locking Capability volatile reprogrammability of the logic, as well as the Three Dedicated Clock Input Pins interconnect to provide truly reconfigurable systems. Synchronous and Asynchronous Clocks The basic unit of logic on these devices is the Generic Programmable Output Slew Rate Control to Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 Minimize Switching Noise (Figure 1). There are a total of eight GLBs in the ispLSI Flexible Pin Placement 2032 and 2032A devices. Each GLB is made up of four Optimized Global Routing Pool Provides Global Interconnectivity macrocells. Each GLB has 18 inputs, a programmable Lead-Free Package Options AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Select devices have been discontinued. See Ordering Information section for product status. Specifications ispLSI 2032/A Functional Block Diagram Figure 1. ispLSI 2032/A Functional Block Diagram GOE 0 I/O 31 I/O 0 I/O 30 I/O 1 A0 A7 I/O 29 I/O 2 I/O 28 I/O 3 I/O 27 I/O 4 I/O 5 I/O 26 Global Routing Pool A1 A6 I/O 6 I/O 25 (GRP) I/O 7 I/O 24 I/O 8 I/O 23 I/O 22 I/O 9 I/O 21 I/O 10 A2 A5 I/O 20 I/O 11 I/O 12 I/O 19 I/O 13 I/O 18 I/O 14 I/O 17 A3 A4 I/O 15 I/O 16 SDI/IN 0 SDO/IN 1 MODE ispEN Y0 Y1*/RESET Notes: SCLK/Y2 *Y1 and RESET are multiplexed on the same pin 0139B(1)isp/2000 The devices also have 32 I/O cells, each of which is All of these signals are made available to the inputs of the directly connected to an I/O pin. Each I/O cell can be GLBs. Delays through the GRP have been equalized to individually programmed to be a combinatorial input, minimize timing skew. output or bi-directional I/O pin with 3-state control. The Clocks in the ispLSI 2032 and 2032A devices are se- signal levels are TTL compatible voltages and the output lected using the dedicated clock pins. Three dedicated drivers can source 4 mA or sink 8 mA. Each output can clock pins (Y0, Y1, Y2) or an asynchronous clock can be be programmed independently for fast or slow output selected on a GLB basis. The asynchronous or Product slew rate to minimize overall output switching noise. Term clock can be generated in any GLB for its own clock. Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032 and 2032A device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. 2 USE ispLSI 2032E FOR NEW DESIGNS Input Bus Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 Output Routing Pool (ORP) Input Bus