ispLSI 2032E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Global Routing Pool A0 A7 (GRP) Small Logic Block Size for Random Logic 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices A1 DQ A6 2 HIGH PERFORMANCE E CMOS TECHNOLOGY DQ Logic fmax = 225 MHz Maximum Operating Frequency A2 GLB Array DQ A5 tpd = 3.5 ns Propagation Delay DQ TTL Compatible Inputs and Outputs A3 A4 5V Programmable Logic Core ispJTAG In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems 0139Bisp/2000 PCI Compatible Outputs (48-Pin Package Only) Open-Drain Output Option Description Electrically Erasable and Reprogrammable Non-Volatile The ispLSI 2032E is a High Density Programmable Logic Unused Product Term Shutdown Saves Power Device. The device contains 32 Registers, 32 Universal ispLSI OFFERS THE FOLLOWING ADDED FEATURES I/O pins, two Dedicated Input Pins, three Dedicated Increased Manufacturing Yields, Reduced Time-to- Clock Input Pins, one dedicated Global OE input pin and Market and Improved Product Quality a Global Routing Pool (GRP). The GRP provides com- Reprogram Soldered Devices for Faster Prototyping plete interconnectivity between all of these elements. OFFERS THE EASE OF USE AND FAST SYSTEM The ispLSI 2032E features 5V in-system programmabil- SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY ity and in-system diagnostic capabilities. The ispLSI OF FIELD PROGRAMMABLE GATE ARRAYS 2032E offers non-volatile reprogrammability of the logic, Complete Programmable Device Can Combine Glue Logic and Structured Designs as well as the interconnect to provide truly reconfigurable Enhanced Pin Locking Capability systems. Three Dedicated Clock Input Pins The basic unit of logic on the ispLSI 2032E device is the Synchronous and Asynchronous Clocks Generic Logic Block (GLB). The GLBs are labeled A0, A1 Programmable Output Slew Rate Control to .. A7 (see Figure 1). There are a total of eight GLBs in the Minimize Switching Noise ispLSI 2032E device. Each GLB is made up of four Flexible Pin Placement macrocells. Each GLB has 18 inputs, a programmable Optimized Global Routing Pool Provides Global Interconnectivity AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually Copyright 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. November 2003 LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2032E Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram GOE 0 I/O 31 I/O 0 I/O 1 I/O 30 A0 A7 I/O 2 I/O 29 I/O 28 I/O 3 I/O 27 I/O 4 I/O 5 I/O 26 Global Routing Pool A1 A6 I/O 6 I/O 25 (GRP) I/O 7 I/O 24 I/O 8 I/O 23 I/O 22 I/O 9 I/O 10 I/O 21 A2 A5 I/O 20 I/O 11 I/O 12 I/O 19 I/O 13 I/O 18 I/O 14 I/O 17 A3 A4 I/O 15 I/O 16 TDI/IN 0 TDO/IN 1 TMS BSCAN Y0 Y1* Notes: TCK/Y2 *Y1 and RESET are multiplexed on the same pin 0139/2032E programmed to be a combinatorial input, output or bi- Clocks in the ispLSI 2032E device are selected using the directional I/O pin with 3-state control. The signal levels dedicated clock pins. Three dedicated clock pins (Y0, Y1, are TTL compatible voltages and the output drivers can Y2) or an asynchronous clock can be selected on a GLB source 4 mA or sink 8 mA. Each output can be pro- basis. The asynchronous or Product Term clock can be grammed independently for fast or slow output slew rate generated in any GLB for its own clock. to minimize overall output switching noise. By connecting Programmable Open-Drain Outputs the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compat- In addition to the standard output configuration, the ible voltages. When connected to a 5V supply, the I/O outputs of the ispLSI 2032E are individually program- pins provide PCI-compatible output drive (48-pin device mable, either as a standard totem-pole output or an only). open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain Eight GLBs, 32 I/O cells, two dedicated inputs and two output drives only the specified Vol. The Voh level on the ORPs are connected together to make a Megablock (see open-drain output depends on the external loading and Figure 1). The outputs of the eight GLBs are connected pull-up. This output configuration is controlled by a pro- to a set of 32 universal I/O cells by the ORP. Each ispLSI grammable fuse. The default configuration when the 2032E device contains one Megablock. device is in bulk erased state is totem-pole configuration. The GRP has as its inputs, the outputs from all of the The open-drain/totem-pole option is selectable through GLBs and all of the inputs from the bi-directional I/O cells. the Lattice software tools. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. 2 Input Bus Output Routing Pool (ORP) CLK 0 CLK 1 CLK 2 Output Routing Pool (ORP) Input Bus