ispLSI 2032VE Device Datasheet June 2010 Select Devices Discontinued Product Change Notification (PCN) 09-10 has been issued to discontinue select devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispLSI 2032VE-110LJ44 ispLSI 2032VE-135LJ44 ispLSI 2032VE-180LJ44 ispLSI 2032VE-225LJ44 ispLSI 2032VE-110LT44 ispLSI 2032VE-135LT44 ispLSI 2032VE-180LT44 ispLSI 2032VE-225LT44 Active / Orderable ispLSI 2032VE-300LT44 ispLSI 2032VE-180LT44I ispLSI 2032VE-110LT48 ispLSI 2032VE-135LT48 ispLSI 2032VE-180LT48 ispLSI 2032VE-225LT48 ispLSI 2032VE-300LT48 ispLSI 2032VE ispLSI 2032VE-110LB49 ispLSI 2032VE-135LB49 ispLSI 2032VE-180LB49 Discontinued PCN 09-10 ispLSI 2032VE-225LB49 ispLSI 2032VE-300LB49 ispLSI 2032VE-110LTN44 ispLSI 2032VE-135LTN44 ispLSI 2032VE-180LTN44 ispLSI 2032VE-300LTN44 ispLSI 2032VE-180LTN44I Active / Orderable ispLSI 2032VE-110LTN48 ispLSI 2032VE-135LTN48 ispLSI 2032VE-180LTN48 ispLSI 2032VE-300LTN48 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Global Routing Pool A0 A7 (GRP) Small Logic Block Size for Random Logic 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V Devices A1 A6 DQ DQ 3.3V LOW VOLTAGE 2032 ARCHITECTURE Logic GLB Interfaces With Standard 5V TTL Devices A2 Array DQ A5 DQ 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A3 A4 fmax = 300 MHz Maximum Operating Frequency tpd = 3.0 ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture 0139Bisp/2000 Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE Description 3.3V In-System Programmability Using Boundary The ispLSI 2032VE is a High Density Programmable Scan Test Access Port (TAP) Logic Device that can be used in both 3.3V and 5V Open-Drain Output Option for Flexible Bus Interface systems. The device contains 32 Registers, 32 Universal Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic I/O pins, two Dedicated Input Pins, three Dedicated Increased Manufacturing Yields, Reduced Time-to- Clock Input Pins, one dedicated Global OE input pin and Market and Improved Product Quality a Global Routing Pool (GRP). The GRP provides Reprogram Soldered Devices for Faster Prototyping complete interconnectivity between all of these elements. The ispLSI 2032VE features in-system programmability 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE through the Boundary Scan Test Access Port (TAP) and THE EASE OF USE AND FAST SYSTEM SPEED OF is 100% IEEE 1149.1 Boundary Scan Testable. The PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs ispLSI 2032VE offers non-volatile reprogrammability of Enhanced Pin Locking Capability the logic, as well as the interconnect to provide truly Three Dedicated Clock Input Pins reconfigurable systems. Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control The basic unit of logic on the ispLSI 2032VE device is the Flexible Pin Placement Generic Logic Block (GLB). The GLBs are labeled A0, A1 Optimized Global Routing Pool Provides Global .. A7 (see Figure 1). There are a total of eight GLBs in the Interconnectivity ispLSI 2032VE device. Each GLB is made up of four Lead-Free Package Options macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556