Select devices have been discontinued. See Ordering Information section for product status. ispLSI 2064/A In-System Programmable High Density PLD Features Functional Block Diagram ENHANCEMENTS ispLSI 2064A is Fully Form and Function Compatible Input Bus to the ispLSI 2064, with Identical Timing Output Routing Pool (ORP) Specifcations and Packaging B7 B6 B5 B4 ispLSI 2064A is Built on an Advanced 0.35 Micron 2 CMOS Technology E Global Routing Pool HIGH DENSITY PROGRAMMABLE LOGIC A0 B3 (GRP) 2000 PLD Gates 64 I/O Pins, Four Dedicated Inputs B2 A1 DQ 64 Registers DQ Logic High Speed Global Interconnect GLB Array A2 DQ B1 Wide Input Gating for Fast Counters, State DQ Machines, Address Decoders, etc. B0 A3 Small Logic Block Size for Random Logic 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A4 A5 A6 A7 fmax = 125 MHz Maximum Operating Frequency Output Routing Pool (ORP) tpd = 7.5 ns Propagation Delay Input Bus TTL Compatible Inputs and Outputs 0139Bisp/2064 Electrically Erasable and Reprogrammable Fu Non-Volatile Description 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power The ispLSI 2064 and 2064A are High Density Program- IN-SYSTEM PROGRAMMABLE mable Logic Devices. The devices contain 64 Registers, In-System Programmable (ISP) 5V Only 64 Universal I/O pins, four Dedicated Input pins, three Increased Manufacturing Yields, Reduced Time-to- Dedicated Clock Input pins, two dedicated Global OE Market and Improved Product Quality input pins and a Global Routing Pool (GRP). The GRP Reprogram Soldered Devices for Faster Prototyping provides complete interconnectivity between all of these OFFERS THE EASE OF USE AND FAST SYSTEM elements. The 2064 and 2064A feature 5V in-system SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY programmability and in-system diagnostic capabilities. OF FIELD PROGRAMMABLE GATE ARRAYS The ispLSI 2064 and 2064A offer non-volatile Complete Programmable Device Can Combine Glue reprogrammability of the logic, as well as the intercon- Logic and Structured Designs nect, to provide truly reconfigurable systems. Enhanced Pin Locking Capability The basic unit of logic on these devices is the Generic Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Logic Block (GLB). The GLBs are labeled A0, A1B7 Programmable Output Slew Rate Control to (Figure 1). There are a total of 16 GLBs in the ispLSI 2064 Minimize Switching Noise and 2064A devices. Each GLB is made up of four Flexible Pin Placement macrocells. Each GLB has 18 inputs, a programmable Optimized Global Routing Pool Provides Global AND/OR/Exclusive OR array, and four outputs which can Interconnectivity be configured to be either combinatorial or registered. Lead-Free Package Options Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Select devices have been discontinued. See Ordering Information section for product status. Specifications ispLSI 2064/A Functional Block Diagram Figure 1. ispLSI 2064/A Functional Block Diagram Generic Logic Input Bus Blocks (GLBs) Output Routing Pool (ORP) Megablock B7 B6 B5 B4 I/O 47 I/O 0 I/O 1 I/O 46 A0 B3 I/O 2 I/O 45 I/O 3 I/O 44 I/O 4 I/O 43 I/O 5 I/O 42 Global Routing Pool A1 B2 I/O 6 I/O 41 (GRP) I/O 7 I/O 40 I/O 8 I/O 39 I/O 9 I/O 38 A2 I/O 10 B1 I/O 37 I/O 11 I/O 36 I/O 12 I/O 35 I/O 13 I/O 34 I/O 14 I/O 33 A3 B0 I/O 15 I/O 32 SCLK/IN 3 SDI/IN 0 A4 A5 A6 A7 MODE/IN 1 SDO/IN 2 Output Routing Pool (ORP) RESET ispEN Input Bus 0139B(1)isp/2064 The devices also have 64 I/O cells, each of which is The GRP has as its inputs, the outputs from all of the directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells. individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the output or bi-directional I/O pin with 3-state control. The GLBs. Delays through the GRP have been equalized to signal levels are TTL compatible voltages and the output minimize timing skew. drivers can source 4 mA or sink 8 mA. Each output can Clocks in the ispLSI 2064 and 2064A devices are se- be programmed independently for fast or slow output lected using the dedicated clock pins. Three dedicated slew rate to minimize overall output switching noise. clock pins (Y0, Y1, Y2) or an asynchronous clock can be Eight GLBs, 32 I/O cells, two dedicated inputs and two selected on a GLB basis. The asynchronous or Product ORPs are connected together to make a Megablock Term clock can be generated in any GLB for its own clock. (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by two ORPs. Each ispLSI 2064 and 2064A device contains two Megablocks. 2 USE ispLSI 2064E FOR NEW DESIGNS GOE 0 Input Bus GOE 1 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 I/O 63 I/O 20 I/O 62 I/O 21 I/O 61 I/O 22 I/O 60 I/O 23 I/O 59 I/O 24 I/O 58 I/O 25 I/O 57 I/O 26 I/O 56 I/O 27 I/O 55 I/O 28 I/O 54 I/O 29 I/O 53 I/O 30 I/O 52 I/O 31 I/O 51 I/O 50 I/O 49 I/O 48 CLK 0 Y0 CLK 1 Y1 CLK 2 Y2 Output Routing Pool (ORP) Input Bus