ispLSI 2064E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC Input Bus 2000 PLD Gates Output Routing Pool (ORP) 64 I/O Pins, Four Dedicated Inputs B7 B6 B5 B4 B7 B6 B5 B4 64 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Global Routing Pool A0 B3 Machines, Address Decoders, etc. (GRP) Small Logic Block Size for Random Logic 100% Functionally and JEDEC Upward Compatible A1 B2 DQ with ispLSI 2064 Devices DQ 2 Logic HIGH PERFORMANCE E CMOS TECHNOLOGY GLB Array DQ B1 A2 fmax = 200 MHz Maximum Operating Frequency tpd = 4.5 ns Propagation Delay DQ TTL Compatible Inputs and Outputs A3 B0 5V Programmable Logic Core ispJTAG In-System Programmable via IEEE 1149.1 A4 A5 A6 A7 (JTAG) Test Access Port Output Routing Pool (ORP) User-Selectable 3.3V or 5V I/O Supports Mixed Input Bus Voltage Systems PCI Compatible Outputs 0139/2064E Open-Drain Output Option Electrically Erasable and Reprogrammable Description Non-Volatile Unused Product Term Shutdown Saves Power The ispLSI 2064E is a High Density Programmable Logic ispLSI OFFERS THE FOLLOWING ADDED FEATURES Device. The device contains 64 Registers, 64 Universal Increased Manufacturing Yields, Reduced Time-to- I/O pins, four Dedicated Input Pins, three Dedicated Market and Improved Product Quality Clock Input Pins, two dedicated Global OE input pins and Reprogram Soldered Devices for Faster Prototyping a Global Routing Pool (GRP). The GRP provides com- OFFERS THE EASE OF USE AND FAST SYSTEM plete interconnectivity between all of these elements. SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY The ispLSI 2064E features 5V in-system programmabil- OF FIELD PROGRAMMABLE GATE ARRAYS ity and in-system diagnostic capabilities. The ispLSI Complete Programmable Device Can Combine Glue 2064E offers non-volatile reprogrammability of the logic, Logic and Structured Designs as well as the interconnect to provide truly reconfigurable Enhanced Pin Locking Capability systems. Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks The basic unit of logic on the ispLSI 2064E device is the Programmable Output Slew Rate Control to Generic Logic Block (GLB). The GLBs are labeled A0, A1 Minimize Switching Noise .. B7 (see Figure 1). There are a total of 16 GLBs in the Flexible Pin Placement ispLSI 2064E device. Each GLB is made up of four Optimized Global Routing Pool Provides Global macrocells. Each GLB has 18 inputs, a programmable Interconnectivity AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2064E Functional Block Diagram Figure 1. ispLSI 2064E Functional Block Diagram Generic Logic Input Bus Blocks (GLBs) Output Routing Pool (ORP) Megablock B7 B6 B5 B4 I/O 47 I/O 0 I/O 1 A0 B3 I/O 46 I/O 2 I/O 45 I/O 3 I/O 44 I/O 4 I/O 43 I/O 5 I/O 42 Global Routing Pool A1 B2 I/O 6 I/O 41 (GRP) I/O 7 I/O 40 I/O 8 I/O 39 I/O 9 I/O 38 A2 B1 I/O 10 I/O 37 I/O 11 I/O 36 I/O 12 I/O 35 I/O 13 I/O 34 I/O 14 I/O 33 A3 B0 I/O 15 I/O 32 TCK/IN 3 TDI/IN 0 A4 A5 A6 A7 TMS/IN 1 TDO/IN 2 Output Routing Pool (ORP) RESET BSCAN Input Bus 0139B(1)isp/2064E The device also has 64 I/O cells, each of which is directly GLBs. Delays through the GRP have been equalized to connected to an I/O pin. Each I/O cell can be individually minimize timing skew. programmed to be a combinatorial input, output or bi- Clocks in the ispLSI 2064E device are selected using the directional I/O pin with 3-state control. The signal levels dedicated clock pins. Three dedicated clock pins (Y0, Y1, are TTL compatible voltages and the output drivers can Y2) or an asynchronous clock can be selected on a GLB source 4 mA or sink 8 mA. Each output can be pro- basis. The asynchronous or Product Term clock can be grammed independently for fast or slow output slew rate generated in any GLB for its own clock. to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, Programmable Open-Drain Outputs I/O output levels can be matched to 5V or 3.3V compat- ible voltages. When connected to a 5V supply, the I/O In addition to the standard output configuration, the pins provide PCI-compatible output drive. outputs of the ispLSI 2064E are individually program- mable, either as a standard totem-pole output or an Eight GLBs, 32 I/O cells, two dedicated inputs and two open-drain output. The totem-pole output drives the ORPs are connected together to make a Megablock (see specified Voh and Vol levels, whereas the open-drain Figure 1). The outputs of the eight GLBs are connected output drives only the specified Vol. The Voh level on the to a set of 32 universal I/O cells by two ORPs. Each open-drain output depends on the external loading and ispLSI 2064E device contains two Megablocks. pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the The GRP has as its inputs, the outputs from all of the device is in bulk erased state is totem-pole configuration. GLBs and all of the inputs from the bi-directional I/O cells. The open-drain/totem-pole option is selectable through All of these signals are made available to the inputs of the the Lattice software tools. 2 GOE 0 Input Bus GOE 1 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 I/O 63 I/O 20 I/O 62 I/O 21 I/O 61 I/O 22 I/O 60 I/O 23 I/O 59 I/O 24 I/O 58 I/O 25 I/O 57 I/O 26 I/O 56 I/O 27 I/O 55 I/O 28 I/O 54 I/O 29 I/O 53 I/O 30 I/O 52 I/O 31 I/O 51 I/O 50 I/O 49 I/O 48 CLK 0 Y0 CLK 1 Y1 CLK 2 Y2 Output Routing Pool (ORP) Input Bus