ispLSI 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SUPERFAST HIGH DENSITY IN-SYSTEM Output Routing Pool (ORP) Output Routing Pool (ORP) PROGRAMMABLE LOGIC C7 C6 C5 C4 C3 C2 C1 C0 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs A0 B7 DQ 96 Registers A1 B6 High Speed Global Interconnect DQ Logic Global Routing Pool Wide Input Gating for Fast Counters, State Array DQ GLB (GRP) A2 B5 Machines, Address Decoders, etc. DQ Small Logic Block Size for Random Logic A3 B4 100% Functional/JEDEC Upward Compatible with A4 A5 A6 A7 B0 B1 B2 B3 ispLSI 2096 Devices 2 Output Routing Pool (ORP) Output Routing Pool (ORP) HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency 0919/2096E tpd = 5.0 ns Propagation Delay TTL Compatible Inputs and Outputs Description 5V Programmable Logic Core ispJTAG In-System Programmable via IEEE 1149.1 The ispLSI 2096E is a High Density Programmable Logic (JTAG) Test Access Port Device. The device contains 96 Registers, 96 Universal User-Selectable 3.3V or 5V I/O Supports Mixed- I/O pins, six Dedicated Input pins, three Dedicated Clock Voltage Systems Input pins, two dedicated Global OE input pins and a PCI Compatible Outputs Global Routing Pool (GRP). The GRP provides complete Open-Drain Output Option interconnectivity between all of these elements. The Electrically Erasable and Reprogrammable ispLSI 2096E features 5V in-system programmability Non-Volatile Unused Product Term Shutdown Saves Power and in-system diagnostic capabilities. The ispLSI 2096E offers non-volatile reprogrammability of all logic, as well ispLSI OFFERS THE FOLLOWING ADDED FEATURES as the interconnect to provide truly reconfigurable sys- Increased Manufacturing Yields, Reduced Time-to- tems. Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping The basic unit of logic on the ispLSI 2096E device is the OFFERS THE EASE OF USE AND FAST SYSTEM Generic Logic Block (GLB). The GLBs are labeled A0, A1 SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY .. C7 (see Figure 1). There are a total of 24 GLBs in the OF FIELD PROGRAMMABLE GATE ARRAYS ispLSI 2096E device. Each GLB is made up of four Complete Programmable Device Can Combine Glue macrocells. Each GLB has 18 inputs, a programmable Logic and Structured Designs AND/OR/Exclusive OR array, and four outputs which can Enhanced Pin Locking Capability be configured to be either combinatorial or Three Dedicated Clock Input Pins registered.Inputs to the GLB come from the GRP and Synchronous and Asynchronous Clocks dedicated inputs. All of the GLB outputs are brought back Programmable Output Slew Rate Control to into the GRP so that they can be connected to the inputs Minimize Switching Noise of any GLB on the device. Flexible Pin Placement Optimized Global Routing Pool Provides Global The device also has 96 I/O cells, each of which is directly Interconnectivity connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi- directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2096E Functional Block Diagram Figure 1. ispLSI 2096E Functional Block Diagram Input Bus Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock Generic Logic C7 C6 C5 C4 C3 C2 C1 C0 Blocks (GLBs) I/O 0 I/O 63 I/O 1 A0 B7 I/O 62 I/O 2 I/O 61 I/O 3 I/O 60 Global I/O 4 I/O 59 I/O 5 I/O 58 A1 Routing B6 I/O 6 I/O 57 I/O 7 I/O 56 Pool I/O 8 I/O 55 (GRP) I/O 9 I/O 54 A2 B5 I/O 10 I/O 53 I/O 11 I/O 52 I/O 12 I/O 51 I/O 13 I/O 50 I/O 14 A3 B4 I/O 49 I/O 15 I/O 48 TDI/IN 0 A4 A5 A6 A7 B0 B1 B2 B3 TMS/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) TDO RESET Input Bus Input Bus BSCAN 0917/2096E the VCCIO pins to a common 5V or 3.3V power supply, Programmable Open-Drain Outputs I/O output levels can be matched to 5V or 3.3V compat- In addition to the standard output configuration, the ible voltages. When connected to a 5V supply, the I/O outputs of the ispLSI 2096E are individually program- pins provide PCI-compatible output drive. mable, either as a standard totem-pole output or an Eight GLBs, 32 I/O cells, two dedicated inputs and two open-drain output. The totem-pole output drives the ORPs are connected together to make a Megablock (see specified Voh and Vol levels, whereas the open-drain Figure 1). The outputs of the eight GLBs are connected output drives only the specified Vol. The Voh level on the to a set of 32 universal I/O cells by the two ORPs. Each open-drain output depends on the external loading and ispLSI 2096E device contains three Megablocks. pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the The GRP has as its inputs, the outputs from all of the device is in bulk erased state is totem-pole configuration. GLBs and all of the inputs from the bi-directional I/O cells. The open-drain/totem-pole option is selectable through All of these signals are made available to the inputs of the the Lattice software tools. GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2096E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. 2 GOE 0 Input Bus GOE 1 Output Routing Pool (ORP) I/O 16 I/O 17 I/O 18 I/O 19 I/O 95 I/O 20 I/O 94 I/O 21 I/O 93 I/O 22 I/O 92 I/O 23 I/O 91 I/O 24 I/O 90 I/O 25 I/O 89 I/O 26 I/O 88 I/O 27 I/O 87 I/O 28 I/O 86 I/O 29 I/O 85 I/O 30 I/O 84 I/O 31 I/O 83 I/O 82 I/O 81 I/O 80 IN 2 TCK/IN 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 79 I/O 36 I/O 78 I/O 77 I/O 37 I/O 38 I/O 76 I/O 39 I/O 75 I/O 40 I/O 74 I/O 41 I/O 73 I/O 42 I/O 72 I/O 43 I/O 71 I/O 44 I/O 70 I/O 45 I/O 69 I/O 46 I/O 68 I/O 47 I/O 67 I/O 66 I/O 65 I/O 64 IN 5 CLK 0 Y0 IN 4 CLK 1 Y1 CLK 2 Y2 Output Routing Pool (ORP) Input Bus