ispLSI 2128E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SUPERFAST HIGH DENSITY IN-SYSTEM Output Routing Pool (ORP) Output Routing Pool (ORP) PROGRAMMABLE LOGIC D7 D6 D5 D4 D3 D2 D1 D0 6000 PLD Gates 128 I/O Pins, Eight Dedicated Inputs A0 C7 128 Registers A1 C6 High Speed Global Interconnect Wide Input Gating for Fast Counters, State DQ A2 C5 Machines, Address Decoders, etc. Small Logic Block Size for Random Logic A3 C4 DQ 100% Functional/JEDEC Upward Compatible with Logic A4 C3 ispLSI 2128 Devices GLB Array DQ 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A5 C2 DQ fmax = 180 MHz Maximum Operating Frequency A6 C1 tpd = 5.0 ns Propagation Delay TTL Compatible Inputs and Outputs A7 C0 Global Routing Pool (GRP) 5V Programmable Logic Core ispJTAG In-System Programmable via IEEE 1149.1 B0 B1 B2 B3 B4 B5 B6 B7 (JTAG) Test Access Port Output Routing Pool (ORP) Output Routing Pool (ORP) User-Selectable 3.3V or 5V I/O Supports Mixed- 0139(9A)/2128 Voltage Systems PCI Compatible Outputs Description Open-Drain Output Option Electrically Erasable and Reprogrammable The ispLSI 2128E is a High Density Programmable Logic Non-Volatile Device. The device contains 128 Registers, 128 Univer- Unused Product Term Shutdown Saves Power sal I/O pins, eight Dedicated Input pins, three Dedicated ispLSI OFFERS THE FOLLOWING ADDED FEATURES Clock Input pins, two dedicated Global OE input pins and Increased Manufacturing Yields, Reduced Time-to- a Global Routing Pool (GRP). The GRP provides com- Market and Improved Product Quality plete interconnectivity between all of these elements. Reprogram Soldered Devices for Faster Prototyping The ispLSI 2128E features 5V in-system programmabil- OFFERS THE EASE OF USE AND FAST SYSTEM ity and in-system diagnostic capabilities. The ispLSI SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY 2128E offers non-volatile reprogrammability of all logic, OF FIELD PROGRAMMABLE GATE ARRAYS as well as the interconnect to provide truly reconfigurable Complete Programmable Device Can Combine Glue systems. Logic and Structured Designs Enhanced Pin Locking Capability The basic unit of logic on the ispLSI 2128E device is the Three Dedicated Clock Input Pins Generic Logic Block (GLB). The GLBs are labeled A0, A1 Synchronous and Asynchronous Clocks .. D7 (see Figure 1). There are a total of 32 GLBs in the Programmable Output Slew Rate Control to ispLSI 2128E device. Each GLB is made up of four Minimize Switching Noise macrocells. Each GLB has 18 inputs, a programmable Flexible Pin Placement AND/OR/Exclusive OR array, and four outputs which can Optimized Global Routing Pool Provides Global be configured to be either combinatorial or Interconnectivity registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 128 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2128E Functional Block Diagram Figure 1. ispLSI 2128E Functional Block Diagram RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock IN 5 Generic Logic D7 D6 D5 D4 D3 D2 D1 D0 Blocks (GLBs) IN 4 I/O 95 C7 I/O 94 I/O 93 I/O 92 I/O 0 A0 I/O 1 I/O 91 C6 I/O 2 I/O 90 I/O 3 I/O 89 I/O 88 I/O 4 I/O 87 A1 I/O 5 I/O 86 I/O 6 C5 I/O 85 I/O 7 I/O 84 I/O 8 I/O 9 I/O 83 A2 I/O 10 I/O 82 C4 I/O 81 I/O 11 Global I/O 80 I/O 12 Routing I/O 79 I/O 13 A3 I/O 78 I/O 14 Pool C3 I/O 77 I/O 15 I/O 76 (GRP) I/O 16 I/O 75 I/O 17 A4 I/O 74 I/O 18 C2 I/O 73 I/O 19 I/O 72 I/O 20 I/O 71 I/O 21 I/O 70 A5 I/O 22 C1 I/O 69 I/O 23 I/O 68 I/O 24 I/O 67 I/O 25 I/O 26 I/O 66 A6 I/O 65 I/O 27 C0 I/O 64 I/O 28 I/O 29 I/O 30 A7 I/O 31 TCK/ IN 0 B0 B1 B2 B3 B4 B5 B6 B7 TMS/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus BSCAN 0139/2128E individually programmed to be a combinatorial input, Clocks in the ispLSI 2128E device are selected using the output or bi-directional I/O pin with 3-state control. The dedicated clock pins. Three dedicated clock pins (Y0, Y1, signal levels are TTL compatible voltages and the output Y2) or an asynchronous clock can be selected on a GLB drivers can source 4 mA or sink 8 mA. Each output can basis. The asynchronous or Product Term clock can be be programmed independently for fast or slow output generated in any GLB for its own clock. slew rate to minimize overall output switching noise. By Programmable Open-Drain Outputs connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or In addition to the standard output configuration, the 3.3V compatible voltages. When connected to a 5V outputs of the ispLSI 2128E are individually program- supply, the I/O pins provide PCI-compatible output drive. mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the Eight GLBs, 32 I/O cells, two dedicated inputs and two specified Voh and Vol levels, whereas the open-drain ORPs are connected together to make a Megablock (see output drives only the specified Vol. The Voh level on the Figure 1). The outputs of the eight GLBs are connected open-drain output depends on the external loading and to a set of 32 universal I/O cells by the two ORPs. Each pull-up. This output configuration is controlled by a pro- ispLSI 2128E device contains four Megablocks. grammable fuse. The default configuration when the The GRP has as its inputs, the outputs from all of the device is in bulk erased state is totem-pole configuration. GLBs and all of the inputs from the bi-directional I/O cells. The open-drain/totem-pole option is selectable through All of these signals are made available to the inputs of the the Lattice software tools. GLBs. Delays through the GRP have been equalized to minimize timing skew. 2 Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) IN 2 IN 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 127 I/O 126 I/O 36 I/O 125 I/O 37 I/O 124 I/O 38 I/O 39 I/O 123 I/O 122 I/O 40 I/O 121 I/O 41 I/O 120 I/O 42 I/O 43 I/O 119 I/O 118 I/O 44 I/O 117 I/O 45 I/O 116 I/O 46 I/O 115 I/O 47 I/O 114 I/O 48 I/O 113 I/O 49 I/O 112 I/O 50 I/O 111 I/O 51 I/O 110 I/O 52 I/O 109 I/O 53 I/O 108 I/O 54 I/O 107 I/O 55 I/O 106 I/O 56 I/O 105 I/O 57 I/O 104 I/O 58 I/O 59 I/O 103 I/O 102 I/O 60 I/O 101 I/O 61 I/O 100 I/O 62 I/O 99 I/O 63 I/O 98 I/O 97 I/O 96 Y0 CLK 0 TDI/IN 7 Y1 CLK 1 TDO/IN 6 CLK 2 Y2 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus