ispLSI 2128VE 3.3V In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram* SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC Output Routing Pool (ORP) Output Routing Pool (ORP) 6000 PLD Gates D7 D6 D5 D4 D3 D2 D1 D0 128 and 64 I/O Pin Versions, Eight Dedicated Inputs 128 Registers A0 C7 High Speed Global Interconnect A1 C6 Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. DQ A2 C5 Small Logic Block Size for Random Logic 100% Functional, JEDEC and Pinout Compatible A3 C4 DQ with ispLSI 2128V Devices Logic A4 C3 Array GLB DQ 3.3V LOW VOLTAGE 2128 ARCHITECTURE Interfaces with Standard 5V TTL Devices A5 C2 DQ 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A6 C1 fmax = 250MHz Maximum Operating Frequency A7 C0 tpd = 4.0ns Propagation Delay Global Routing Pool (GRP) Electrically Erasable and Reprogrammable B0 B1 B2 B3 B4 B5 B6 B7 Non-Volatile Output Routing Pool (ORP) Output Routing Pool (ORP) 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power 0139A/2128VE *128 I/O Version Shown IN-SYSTEM PROGRAMMABLE Description 3.3V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP) The ispLSI 2128VE is a High Density Programmable Open-Drain Output Option for Flexible Bus Interface Logic Device available in 128 and 64 I/O-pin versions. Capability, Allowing Easy Implementation of Wired- The device contains 128 Registers, eight Dedicated OR Bus Arbitration Logic Input pins, three Dedicated Clock Input pins, two dedi- Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality cated Global OE input pins and a Global Routing Pool Reprogram Soldered Devices for Faster Prototyping (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128VE 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE features in-system programmability through the Bound- THE EASE OF USE AND FAST SYSTEM SPEED OF ary Scan Test Access Port (TAP) and is 100% IEEE PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS 1149.1 Boundary Scan Testable. The ispLSI 2128VE Enhanced Pin Locking Capability offers non-volatile reprogrammability of the logic, as well Three Dedicated Clock Input Pins as the interconnect to provide truly reconfigurable sys- Synchronous and Asynchronous Clocks tems. Programmable Output Slew Rate Control Flexible Pin Placement The basic unit of logic on the ispLSI 2128VE device is the Optimized Global Routing Pool Provides Global Generic Logic Block (GLB). The GLBs are labeled A0, A1 Interconnectivity .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VE device. Each GLB is made up of four LEAD-FREE PACKAGE OPTIONS macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2128VE Functional Block Diagram Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions) RESET RESET Input Bus Input Bus GOE 0 GOE 0 GOE 1 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock Megablock IN 5 IN 5* Generic Logic Generic Logic D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Blocks (GLBs) IN 4 Blocks (GLBs) IN 4* I/O 95 I/O 47 C7 C7 I/O 94 I/O 46 I/O 93 I/O 45 I/O 92 I/O 44 I/O 0 I/O 0 A0 A0 I/O 1 I/O 91 I/O 1 C6 C6 I/O 2 I/O 90 I/O 2 I/O 3 I/O 89 I/O 3 I/O 88 I/O 4 A1 I/O 87 A1 I/O 43 I/O 5 I/O 86 I/O 42 I/O 6 C5 C5 I/O 85 I/O 41 I/O 7 I/O 84 I/O 40 I/O 8 I/O 4 I/O 83 I/O 9 I/O 5 A2 A2 I/O 82 I/O 6 I/O 10 C4 C4 I/O 11 Global I/O 81 I/O 7 Global I/O 80 I/O 12 Routing Routing I/O 79 I/O 13 A3 A3 I/O 78 I/O 14 Pool C3 C3 Pool I/O 77 I/O 15 I/O 76 I/O 16 (GRP) (GRP) I/O 75 I/O 39 I/O 17 A4 A4 I/O 74 I/O 38 I/O 18 C2 C2 I/O 73 I/O 37 I/O 19 I/O 72 I/O 36 I/O 20 I/O 8 I/O 71 I/O 9 I/O 21 A5 I/O 70 I/O 10 A5 I/O 22 I/O 69 C1 I/O 11 C1 I/O 23 I/O 68 I/O 24 I/O 25 I/O 67 I/O 35 I/O 26 I/O 66 I/O 34 A6 A6 I/O 27 C0 I/O 65 I/O 33 C0 I/O 64 I/O 32 I/O 12 I/O 28 I/O 13 I/O 29 I/O 30 I/O 14 A7 A7 I/O 31 I/O 15 TDI/IN 0 TDI/IN 0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B7 B2 B3 B4 B5 B6 TMS/IN 1 TMS/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus BSCAN BSCAN 0139B/2128VE 0139B/2128VE.64IO *Not available on 84-PLCC Device The 128-I/O 2128VE contains 128 I/O cells, while the 64- Y1, Y2) or an asynchronous clock can be selected on a I/O version contains 64 I/O cells. Each I/O cell is directly GLB basis. The asynchronous or Product Term clock connected to an I/O pin and can be individually pro- can be generated in any GLB for its own clock. grammed to be a combinatorial input, output or Programmable Open-Drain Outputs bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers In addition to the standard output configuration, the can source 4mA or sink 8mA. Each output can be outputs of the ispLSI 2128VE are individually program- programmed independently for fast or slow output slew mable, either as a standard totem-pole output or an rate to minimize overall output switching noise. Device open-drain output. The totem-pole output drives the pins can be safely driven to 5V signal levels to support specified Voh and Vol levels, whereas the open-drain mixed-voltage systems. output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and pull-up. This output configuration is controlled by a pro- two or one ORPs are connected together to make a grammable fuse. The default configuration when the Megablock (see Figure 1). The outputs of the eight GLBs device is in bulk erased state is totem-pole configuration. are connected to a set of 32 or 16 universal I/O cells by The open-drain/totem-pole option is selectable through the two or one ORPs. Each ispLSI 2128VE device the Lattice software tools. contains four Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, 2 Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) TDO/IN 2 TCK/IN 3 I/O 32 I/O 33 I/O 34 I/O 35 I/O 127 I/O 126 I/O 36 I/O 125 I/O 37 I/O 124 I/O 38 I/O 123 I/O 39 I/O 122 I/O 40 I/O 121 I/O 41 I/O 120 I/O 42 I/O 119 I/O 43 I/O 118 I/O 44 I/O 117 I/O 45 I/O 116 I/O 46 I/O 47 I/O 115 I/O 114 I/O 48 I/O 113 I/O 49 I/O 112 I/O 50 I/O 51 I/O 111 I/O 110 I/O 52 I/O 109 I/O 53 I/O 108 I/O 54 I/O 107 I/O 55 I/O 106 I/O 56 I/O 105 I/O 57 I/O 104 I/O 58 I/O 59 I/O 103 I/O 102 I/O 60 I/O 101 I/O 61 I/O 100 I/O 62 I/O 63 I/O 99 I/O 98 I/O 97 I/O 96 Y0 CLK 0 IN 7 Y1 CLK 1 IN 6 Y2 CLK 2 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus Input Bus Output Routing Pool (ORP) TDO/IN 2 TCK/IN 3 I/O 16 I/O 17 I/O 18 I/O 19 I/O 63 I/O 62 I/O 61 I/O 60 I/O 20 I/O 21 I/O 22 I/O 23 I/O 59 I/O 58 I/O 57 I/O 56 I/O 24 I/O 25 I/O 26 I/O 27 I/O 55 I/O 54 I/O 53 I/O 52 I/O 28 I/O 29 I/O 30 I/O 31 I/O 51 I/O 50 I/O 49 I/O 48 CLK 0 Y0 IN 7* Y1 CLK 1 IN 6* Y2 CLK 2 Output Routing Pool (ORP) Input Bus