ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC Output Routing Pool Output Routing Pool 8000 PLD Gates F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 96 I/O Pins, Nine or Twelve Dedicated Inputs A0 D7 192 Registers DQ D6 A1 High Speed Global Interconnect A2 D5 DQ Logic Wide Input Gating for Fast Counters, State A3 D4 Global Routing Pool (GRP) GLB Array A4 DQ D3 Machines, Address Decoders, etc. A5 D2 Small Logic Block Size for Random Logic DQ A6 D1 Pinout Compatible with ispLSI 2096V and 2096VE A7 D0 3.3V LOW VOLTAGE ARCHITECTURE B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 Interfaces with Standard 5V TTL Devices Output Routing Pool Output Routing Pool 2 HIGH PERFORMANCE E CMOS TECHNOLOGY 0139/2192VE fmax = 225MHz Maximum Operating Frequency tpd = 4.0ns Propagation Delay Description Electrically Erasable and Reprogrammable Non-Volatile The ispLSI 2192VE is a High Density Programmable 100% Tested at Time of Manufacture Logic Device containing 192 Registers, nine or twelve Unused Product Term Shutdown Saves Power Dedicated Input pins, three Dedicated Clock Input pins, IN-SYSTEM PROGRAMMABLE two dedicated Global OE input pins and a Global Routing 3.3V In-System Programmability (ISP) Using Pool (GRP). The GRP provides complete interconnectivity Boundary Scan Test Access Port (TAP) between all of these elements. The ispLSI 2192VE Open-Drain Output Option for Flexible Bus Interface features in-system programmability through the Bound- Capability, Allowing Easy Implementation of Wired- ary Scan Test Access Port (TAP) and is 100% IEEE OR Bus Arbitration Logic 1149.1 Boundary Scan Testable. The ispLSI 2192VE Increased Manufacturing Yields, Reduced Time-to- offers non-volatile reprogrammability of the logic, as well Market and Improved Product Quality as the interconnect to provide truly reconfigurable sys- Reprogram Soldered Devices for Faster Prototyping tems. 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE The basic unit of logic on the ispLSI 2192VE device is the THE EASE OF USE AND FAST SYSTEM SPEED OF Generic Logic Block (GLB). The GLBs are labeled A0, A1 PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS .. F7 (see Figure 1). There are a total of 48 GLBs in the Enhanced Pin Locking Capability ispLSI 2192VE device. Each GLB is made up of four Three Dedicated Clock Input Pins macrocells. Each GLB has 18 inputs, a programmable Synchronous and Asynchronous Clocks AND/OR/Exclusive OR array, and four outputs which can Programmable Output Slew Rate Control be configured to be either combinatorial or registered. Flexible Pin Placement Inputs to the GLB come from the GRP and dedicated Optimized Global Routing Pool Provides Global Interconnectivity inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any LEAD-FREE PACKAGE OPTIONS GLB on the device. Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 2192VE Functional Block Diagram Figure 1. ispLSI 2192VE Functional Block Diagram I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 11* 10 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8 RESET Input Bus Input Bus GOE 0 Generic Output Routing Pool (ORP) Output Routing Pool (ORP) GOE 1 Logic Blocks (GLBs) IN 7/TCK F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 IN 6/TDO I/O 63 D7 I/O 62 I/O 61 I/O 0 A0 D6 I/O 60 I/O 1 I/O 2 I/O 59 I/O 3 A1 D5 I/O 58 I/O 57 I/O 4 Global A2 D4 I/O 56 I/O 5 I/O 6 Routing A3 I/O 55 I/O 7 D3 Pool I/O 54 I/O 53 I/O 8 A4 D2 (GRP) I/O 52 I/O 9 I/O 10 A5 I/O 51 I/O 11 D1 I/O 50 I/O 49 I/O 12 A6 D0 I/O 13 I/O 48 I/O 14 A7 I/O 15 TDI/IN 0 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 TMS/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock Input Bus Input Bus BSCAN IN 2* IN 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN4 IN 5* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Y0 Y1 Y2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 *Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages. 2192VE Block.eps The 2192VE contains 96 I/O cells. Each I/O cell is directly Clocks in the ispLSI 2192VE device are selected using connected to an I/O pin and can be individually pro- the dedicated clock pins. Three dedicated clock pins (Y0, grammed to be a combinatorial input, output or Y1, Y2) or an asynchronous clock can be selected on a bi-directional I/O pin with 3-state control. The signal GLB basis. The asynchronous or Product Term clock levels are TTL compatible voltages and the output drivers can be generated in any GLB for its own clock. can source 4mA or sink 8mA. Each output can be Programmable Open-Drain Outputs programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device In addition to the standard output configuration, the pins can be safely driven to 5V signal levels to support outputs of the ispLSI 2192VE are individually program- mixed-voltage systems. mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the Eight GLBs, 16 I/O cells, two dedicated inputs and an specified Voh and Vol levels, whereas the open-drain ORP are connected together to make a Megablock (see output drives only the specified Vol. The Voh level on the Figure 1). The outputs of the eight GLBs are connected open-drain output depends on the external loading and to a set of 16 universal I/O cells by the ORP. Each ispLSI pull-up. This output configuration is controlled by a pro- 2192VE device contains six Megablocks. grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The GRP has as its inputs, the outputs from all of the The open-drain/totem-pole option is selectable through GLBs and all of the inputs from the bi-directional I/O cells. the Lattice software tools. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. 2 Input Bus Output Routing Pool (ORP) CLK 0 CLK 1 Output Routing Pool (ORP) CLK 2 lnput Bus